International audienceThis paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing: 1) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics; 2) descriptions of ambipolar behavior in Schottky-barrier CNTFETs and ambivalence in double-gate CNTFETs (DG-CNTFETs). Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of DG-CNTFETs in fine-grain reconfigurable logic
During the last years, Graphene based Field Effect Transistors (GFET) have
shown outstanding RF performance; therefore, they have attracted considerable
attention from the electronic devices and circuits communities. At the same
time, analytical models that predict the electrical characteristics of GFETs
have evolved rapidly. These models, however, have a complexity level that can
only be handled with the help of a circuit simulator. On the other hand, analog
circuit designers require simple models that enable them to carry out fast hand
calculations, i.e., to create circuits using small-signal hybrid-{\pi} models,
calculate figures of merit, estimate gains, pole-zero positions, etc. This
paper presents a comprehensive GFET model that is simple enough for being used
in hand-calculations during circuit design and at the same time it is accurate
enough to capture the electrical characteristics of the devices in the
operating regions of interest. Closed analytical expressions are provided for
the drain current ID, small-signal transconductance gain gm, output resistance
ro, and parasitic Vgs and Cgd. In addition, figures of merit such as intrinsic
voltage gain AV, transconductance efficiency gm/ID, and transit frequency fT
are presented. The proposed model has been compared to a complete analytical
model and also to measured data available in current literature. The results
show that the proposed model follows closely to both the complete analytical
model and the measured data; therefore, it can be successfully applied in the
design of GFET analog circuits.Comment: 9 pages,11 figure
This paper investigates on-wafer characterization of SiGe HBTs up to 500 GHz. Test structures for on-wafer TRL calibration have been designed and are presented. The TRL calibration method with silicon standards has first been benchmarked through EM-simulation. Passive and active components are then characterized up to 500 GHz. The slight discontinuities between the frequency bands are explored. A specific focus was placed on incorrect horizontal probe positioning as well as on probe deformation, resulting in a better assessment of possible measurement errors.
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