Analysis and verification of interconnected rings as clock distribution networks

Abstract

The use of interconnected rings approach, as globally asynchronous, locally synchronous clock distribution network, offers good performance regarding scalability, low clock-skew and high-speed clocking. Moreover, they show linear metal-cost growth and the power consumption is directly proportional to number of interconnected rings. In this paper, the performance of interconnected rings, working as clock distribution networks, is analyzed and verified by experimental measurements. Typical 3.3V 0.35µm CMOS N-well AMS process parameters were used for the analysis and chip fabrication. It is shown that interconnected rings are a robust approach under parameters variations.

VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

“…This, however, comes at the price of a reduction of clock accurracy and stability. [19,20] presents an alternative approach for generating and distributing GHz clocks. The design relies on the self-oscillation property when interconnecting an odd number of inverters in a ring topology (shown in Figure 2) and achieves high clock frequencies due to its simplicity.…”

“Swimming pool”-like distributed architecture for clock generation in large many-core SoC

“…This study focuses on study and design of distributed clock generators, whose basic idea was presented in [5] [6]. Each local clock area has its clock generator coupled in phase with the clock generators in neighboring areas.…”