VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

Abstract

We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on the hardware implementation of a tick synchronization algorithm from the distributed systems community. We discuss the selection of an appropriate algorithm, present the refinement steps necessary to facilitate its efficient mapping to hardware, and elaborate on the key challenges we had to overcome in our actual ASIC implementation. Our measurement results confirm that the approach is indeed capable of creating a globally synchronized clock in a distributed fashion that is tolerant to a (configurable) number of arbitrary faults. This property facilitates eliminating the clock as a single point of failure. Our solution is based on purely asynchronous design, obviating the need for crystal oscillators. It is capable of adapting to parameter variations as well as changes in temperature and power supply-properties that are considered highly desirable for future technology nodes.

An infrastructure for accurate characterization of single-event transients in digital circuits

“…Moreover, asynchrony is also a quite natural phenomenon at higher system layers, as in Globally Asynchronous, Locally Synchronous (GALS) architectures [5] , for example. Unfortunately, unlike for synchronous systems, fault-tolerance is difficult to guarantee in asynchronous systems [6] , and has hence not received much attention in asynchronous digital circuits [7–10,1,11] .…”

Reconciling fault-tolerant distributed computing and systems-on-chip

“…The DARTS clocking scheme has been implemented both in an FPGA [20] and in a custom radiation-hardened ASIC [24,27], which proves that the approach is feasible in practice and indeed works very well. Although the implementation complexity of DARTS is definitely not negligible, it must be considered as the price for a fault-tolerant clocking system.…”