The performance of interconnected rings and oscillators, working as clock distribution networks, is analyzed and compared among several configurations. The use of interconnected 3-inverter rings as globally asynchronous, locally synchronous clock distribution networks is proposed even for chip lengths from 4 to 24 mm. In this approach, modularity and basic cell properties are kept while the power consumption results directly proportional to the number of blocks. Typical 3.3V AMS 0.35µm CMOS N-well process parameters were used for the analysis. Regarding the current area expansion, we show that interconnected rings is a more robust approach than the interconnected oscillators.
In this paper the most interesting topologies of one-bit hybrid full adders, are analyzed and compared for speed, power consumption, and power-delay product. The investigation has been carried out with properly defined simulation set up and input pattern on a Mentor Graphics environment using a TSMC 180 nm CMOS process. Performance has been also compared for different supply voltage values. The simulation results show that the Chang adder is the best in terms of PDP figure of merit; however the Aguirre adder is the best in terms of driving capability even at low power supply.
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