Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outside the vehicle. The AES algorithm has been widely applied to protect communications in onboard networks and outside the vehicle. Hardware implementations use techniques such as iterative, parallel, unrolled, and pipeline architectures. Nevertheless, the use of AES does not guarantee secure communication, because previous works have proved that implementations of secret key cryptosystems, such as AES, in hardware are sensitive to differential fault analysis. Moreover, it has been demonstrated that even a single fault during encryption or decryption could cause a large number of errors in encrypted or decrypted data. Although techniques such as iterative and parallel architectures have been explored for fault detection to protect AES encryption and decryption, it is necessary to explore other techniques such as pipelining. Furthermore, balancing a high throughput, reducing low power consumption, and using fewer hardware resources in the pipeline design are great challenges, and they are more difficult when considering fault detection and correction. In this research, we propose a novel hybrid pipeline hardware architecture focusing on error and fault detection for the AES cryptographic algorithm. The architecture is hybrid because it combines hardware and time redundancy through a pipeline structure, analyzing and balancing the critical path and distributing the processing elements within each stage. The main contribution is to present a pipeline structure for ciphering five times on the same data blocks, implementing a voting module to verify when an error occurs or when output has correct cipher data, optimizing the process, and using a decision tree to reduce the complexity of all combinations required for evaluating. The architecture is analyzed and implemented on several FPGA technologies, and it reports a throughput of 0.479 Gbps and an efficiency of 0.336 Mbps/LUT when a Virtex-7 is used.
Next generation sequencing technologies have noticeably improved in the last decade. Time and cost of whole genome sequencing are important challenges that must be reduced, opening unprecedented opportunities to various research and development areas. The alignment or mapping of small reads produced by sequencing machines to reference genomes of billions of nucleotides is a fundamental task in this sequencing process. It is computationally highly demanding and has become the bottleneck of the DNA analysis process. This paper proposes hardware acceleration based on FPGA of the Myers bit-parallelized algorithm, appropriately modified to be used in the extend stage of DNA alignment tools. The proposed design can be employed in conjunction with software functions, as it constitutes an extremely fast heterogeneous DNA alignment system. The implementation results show a speedup of up to [Formula: see text] relative to a sequential implementation only in software. In addition, due to the limited use of FPGA resources and the modular design, multiple modules can be used to completely populate the chip, further increasing the computing speed.
Shoeprint marks present valuable information for forensic investigators to resolve a crime. These marks can be helpful to find the brand of the shoe and can make the investigation easier. In this paper, we present an associative model-based algorithm to match noisy shoeprint patterns with a brand of shoe. The shoeprints are corrupted with additive, subtractive and mixed noises. A particular case of subtractive noise are partial shoeprints such as toe, heel, left-half and right-half prints. The Morphological Associative Memories (MAMs) were applied. Both memories, max and min, recognize noisy shoeprints corrupted with 98% additive and subtractive noise, respectively, with an effectiveness of 100%. The images corrupted with mixed noise were recognized when the additive or subtractive noise applied was greater than the mixed noise; in this case, the recalling was around 70%, otherwise, both memories failed to recognize the shoeprints.
Los beneficios atribuidos a la realidad aumentada (RA) en la enseñanza de diferentes campos del conocimiento, han propiciado la intersección de modalidades y métodos de enseñanza aprendizaje que buscar potencializar las fortalezas de dicha tecnología aplicada en la educación. Uno de estos enfoques, entrelaza a la realidad aumentada con el aprendizaje móvil y con el aprendizaje basado en las simulaciones. No obstante, el cómo desarrollar estas aplicaciones a fin que permitan proporcional una experiencia de aprendizaje, es una línea que continúa construyéndose. En este artículo se presentan las fases de desarrollo de un simulador en realidad aumentada móvil, cuya formulación parte de la experiencia de un grupo de estudiantes al usar un simulador web. Además, se presentan los resultados de la evaluación de la calidad de los objetos de realidad aumentada, obteniendo una valoración positiva en los aspectos técnicos, de utilización y guía, lo que sugiere una integración adecuada de tecnología de realidad aumentada con los aspectos pedagógicos considerados en el diseño de la aplicación.
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