Bit-Vector-Based Hardware Accelerator for DNA Alignment Tools

Abstract

Next generation sequencing technologies have noticeably improved in the last decade. Time and cost of whole genome sequencing are important challenges that must be reduced, opening unprecedented opportunities to various research and development areas. The alignment or mapping of small reads produced by sequencing machines to reference genomes of billions of nucleotides is a fundamental task in this sequencing process. It is computationally highly demanding and has become the bottleneck of the DNA analysis process. This paper proposes hardware acceleration based on FPGA of the Myers bit-parallelized algorithm, appropriately modified to be used in the extend stage of DNA alignment tools. The proposed design can be employed in conjunction with software functions, as it constitutes an extremely fast heterogeneous DNA alignment system. The implementation results show a speedup of up to [Formula: see text] relative to a sequential implementation only in software. In addition, due to the limited use of FPGA resources and the modular design, multiple modules can be used to completely populate the chip, further increasing the computing speed.

OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors

“…Not only we are able to address much bigger designs up to 300 × 360, but in comparison, for designs of 100 × 100 we get up to 91.5 MPPS in HARPv2. A recent work from Bautista [8] does not provide an improvement in terms of performance. On the other hand, he provides the backtrace.…”

“…Some FPGA implementations of the Myers algorithm have been proposed in the literature [7], [8]. In [10], Hyyrö proposes a bit-vector algorithm to compute the semi-global distance below a threshold k. It is based on Myers' binary equations and uses a banded matrix to reduce the required computation.…”

“…Some mappers incorporate the idea of using less computationalintensive alternatives to SW and use pre-alignment filters to discard alignment candidates, hence, moving from the SE approach to the Seed-Filter-and-Extend (SFE) approach. Among other algorithms, the filtering phase might use Bit-Parallel Myers (BPM) [3], which has been optimized for CPUs [4], [5], GPUs [6], and FPGAs [7], [8]. However, the SFE approach introduce some constraints that allow optimizations to be applied that are not considered when using the BPM technique.…”

FPGA Acceleration of Pre-Alignment Filters for Short Read Mapping With HLS

“…The dynamic programming approach to compute the Levenshtein distance is often perceived as too slow and not scalable enough for fast evaluation of the similarity between two strings. However, some implementations of the Levenshtein distance have been successfully implemented in FPGAs achieving high performance like [29], and [30].…”