International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)
DOI: 10.1109/iedm.1998.746382
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An ultra-low resistance and thermally stable W/pn-poly-Si gate CMOS technology using Si/TiN buffer layer

Hitoshi Wakabayashi
1
,
Tetsuya Yamamoto2,
K. Yoshida3
et al.
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