Sub-50-nm physical gate length CMOS technology and beyond using steep halo

Wakabayashi, Hitoshi; Ueki, Makoto; Narihiro, M.; Fukai, T.; Ikezawa, N.; Matsuda, Tomoko; Yoshida, K.; Takeuchi, Kiyoshi; Ochiai, Yukinori; Mogami, Tohru; Kunio, Takeshi

doi:10.1109/16.974754

Cited by 36 publications

(8 citation statements)

References 9 publications

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“…1,2 Recently, advances have focused on channel engineering utilizing superhalo ion implantation, which results in both vertically and laterally nonuniform two-dimensional ͑2-D͒ profiles to overcome short channel effects. 3,4 Cross-sectional scanning capacitance microscopy ͑SCM͒ 5 and spectroscopy 6 have been used as powerful metrology tools in actual Si device structures. We have used SCM imaging, over a range of applied sample bias voltages, to clearly delineate the individual device regions in a deep-submicron p-channel Si metal-oxide-semiconductor field-effect transistor (p-MOSFET), including n ϩ superhalo implants.…”

Section: Department Of Electrical and Computer Engineering And Materimentioning

confidence: 99%

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Direct measurement and characterization of n+ superhalo implants in a 120 nm gate-length Si metal–oxide–semiconductor field-effect transistor using cross-sectional scanning capacitance microscopy

Rosenthal

Taur

2002

Applied Physics Letters

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Articles you may be interested inTwo-dimensional characterization of carrier concentration in metal-oxide-semiconductor field-effect transistors with the use of scanning tunneling microscopy Visualization of 0.1-μm-metal-oxide-semiconductor field-effect transistors by cross-sectional scanning tunneling microscopy Appl. Phys. Lett. 81, 2475 (2002); 10.1063/1.1509118Boron penetration in p-channel metal-oxide-semiconductor field-effect transistors enhanced by gate ionimplantation damage Two dimensional dopant and carrier profiles obtained by scanning capacitance microscopy on an actively biased cross-sectioned metal-oxide-semiconductor field-effect transistor Comparison of two-dimensional carrier profiles in metal-oxide-semiconductor field-effect transistor structures obtained with scanning spreading resistance microscopy and inverse modeling

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Section: Department Of Electrical and Computer Engineering And Materimentioning

confidence: 99%

“…Additional details of the device fabrication process are described elsewhere. 3,4 The sample was prepared for imaging using established SCM cross-sectional sample preparation techniques. 6 regions.…”

Section: Department Of Electrical and Computer Engineering And Materimentioning

confidence: 99%

Direct measurement and characterization of n+ superhalo implants in a 120 nm gate-length Si metal–oxide–semiconductor field-effect transistor using cross-sectional scanning capacitance microscopy

Rosenthal

Taur

2002

Applied Physics Letters

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“…TCAD provides a direct method to explore, optimize and control processes to achieve the desired properties of the key components. Shallow junction formation is a hot topic in semiconductor industry and has been a very crucial process step in future CMOS generation [1,4]. As transistors are made smaller, the junctions that form the source and drain regions of the transistor must be made shallower to improve the performance and provide sufficient breakdown characteristics.…”

Section: Introductionmentioning

confidence: 99%

Low Resistance Electrical Layer Formation: A Simulation Study of Diffusive Rapid Thermal Process on Implanted Dopant Species for Electronics Active Devices

Adam

Hashim

2012

2012 Fourth International Conference on Computational Intelligence, Modelling and Simulation

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A simple and economical spin-on-dopants simulation technique for ultra thin layer formation is presented; the Ultra thin for the purpose of shallow junction formation in large scaled integrated technology is one of the most challenging in device fabrication. Low energy ion implantation is the most widely used technique at present to form ultra shallow junction but this method has some limitations such as silicon surface damage, however, many attempt have been made to overcome this but it seems difficult to do away with this limitation. An ultra high shallow junction formation of < 20 nm was proposed through thermal diffusion from spin-on dopants into silicon, the study presented a determination of the junction depth and the sheet resistance of the shallow junction in order to fulfill the standard semiconductor device design requirements. Ultra shallow junction which is defined to be less than 20 nm in depth was obtained through this simulation using very simple and easy spin-on dopants technique.

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“…The continuation of these improvements will require the production of ultra-shallow junctions for the source/drain extension regions using low energy ion-implantation [1]. Strain engineering using Si/SiGe heterostructures has become a key technology for the enhancement of device operating speeds [4].…”

Section: Introductionmentioning

confidence: 99%