An SOI-based three-dimensional integrated circuit technology

Burns, James R.; McIlrath, L.; Hopwood, Jeffrey; Keast, C.L.; Vu, D.P.; Warner, K.; Wyatt, P.W.

doi:10.1109/soi.2000.892749

Cited by 28 publications

(8 citation statements)

References 1 publication

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“…However, implementing such an approach requires the density of the vertical interconnection to the top layers to be comparable to that of the via density in the CMOS technology used to implement the LBs and interconnects. Several approaches to chip-and wafer-stacked 3-D integrated circuits (3-D IC) have been recently developed [10], [11]. The vertical via densities achieved by these technologies, however, are several orders of magnitude lower than that of a state-of-the-art CMOS technology, and they are not expected to scale much.…”

Section: A Monolithically Stacked 3-d Fpgamentioning

confidence: 99%

Performance benefits of monolithically stacked 3D-FPGA

Lin

Gamal

et al. 2006

Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays

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Abstract-The performance benefits of a monolithically stacked three-dimensional (3-D) field-programmable gate array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing logic blocks (LBs) and interconnects, are investigated. A Virtex-II-style two-dimensional (2-D) FPGA fabric is used as a baseline architecture to quantify the relative improvements in logic density, delay, and power consumption achieved by such a 3-D FPGA. It is assumed that only the switch transistor and configuration memory cells can be moved to the top layers and that the 3-D FPGA employs the same LB and programmable interconnect architecture as the baseline 2-D FPGA. Assuming they are ≤ 0.7, the area of a static random-access memory cell and switch transistors having the same characteristics as n-channel metal-oxide-semiconductor devices in the CMOS layer are used. It is shown that a monolithically stacked 3-D FPGA can achieve 3.2 times higher logic density, 1.7 times lower critical path delay, and 1.7 times lower total dynamic power consumption than the baseline 2-D FPGA fabricated in the same 65-nm technology node.

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Section: A Monolithically Stacked 3-d Fpgamentioning

confidence: 99%

Performance benefits of monolithically stacked 3D-FPGA

Lin

Gamal

et al. 2006

Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays

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“…In our experiments we used the 3D FPGA architecture of Figure 1(a) where segment lengths of 1, 2, and "long" 4 form the inter-tier routing structure, and segment lengths of 1, 2, 6, and "long" are used within tiers. The delay of an intertier segment is assumed to be equal to that of an intra-tier segment of the same length.…”

Section: Fpga Resultsmentioning

confidence: 99%

“…Consequently, 3D integration can be an enabler for enhancements in system performance, power, reliability, and portability. Advances in industrial [3], government [4] and academic [5] research laboratories have demonstrated 3D designs with inter-tier separations of the order of a few microns. Recently, MIT Lincoln Laboratories has offered a MOSIS-like 3D integration program under the auspices of DARPA.…”

Section: Introductionmentioning

confidence: 99%

Placement and Routing in 3D Integrated Circuits

Ababei

Feng²,

Goplen

et al. 2005

IEEE Des. Test. Comput.

136

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Abstract-Advances in the chip fabrication technology have begun to make manufacturing 3D chips a reality. The road ahead presents many challenges both in the technology and the EDA domains before potential benefits of tightly integrated 3D systems can be reaped. We present our placement and routing algorithms for 3D FPGA and ASIC designs. Our method addresses wire length, delay and area minimization, as well as thermal optimization during placement and routing phases. These flows have been used to obtain optimized layouts for benchmarks with tens to hundreds of thousands of cells.

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“…These techniques vary in terms of their baseline characteristics such as interlayer interconnect lengths and bandwidth, and therefore, in the architectural features that they enable. References [15][16][17][18][19][20][21][22][23] provide a good overview of the current 3D manufacturing techniques. We focus on wafer-and chip-level parallel integration for the rest of the discussion.…”

Section: D Integration Technology: Preliminariesmentioning

confidence: 99%