An overview of the COBRA-ABS high level synthesis system for multi-FPGA systems

Duncan, Andrew A.; Hendry, D.; Gray, Peter

doi:10.1109/fpga.1998.707888

Cited by 19 publications

(17 citation statements)

References 15 publications

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“…In [35], a layout-driven high-level synthesis approach is presented to reduce the gap between metrics predicted during RTL synthesis and the measured data after FPGA implementation. High-level synthesis for a multi-FPGA system is done in [14]. On the low-power part, [34] takes an RTL design and trades off power with circuit speed by selecting different implementations of components iteratively.…”

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confidence: 99%

LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization

Chen

Cong

Fan³

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. LOPASS includes three major components: 1) a flexible high-level power estimator for FPGAs considering the power consumption of various FPGA logic components and interconnects; 2) a simulated-annealing optimization engine that carries out resource selection and allocation, scheduling, functional unit binding, register binding, and interconnection estimation simultaneously to reduce power effectively; and 3) a -cofamily-based register binding algorithm and an efficient port assignment algorithm that reduce interconnections in the data path through multiplexer optimization. The experimental results show that LOPASS produces promising results on latency optimization compared to an academic high-level synthesis tool SPARK. Compared to an early commercial high-level synthesis tool, namely, Synopsys Behavioral Compiler, LOPASS is 61.6% better on power consumption and 10.6% better on clock period on average. Compared to a current commercial tool, namely, Impulse C, LOPASS is 31.1% better on power reduction with an 11.8% penalty on clock period.Index Terms-Behavioral synthesis, field-programmable gate array (FPGA), interconnect, power optimization.

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confidence: 99%

LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization

Chen

Cong

Fan³

et al. 2010

IEEE Trans. VLSI Syst.

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“…The simulated annealing algorithm has been proved efficient for high-level synthesis to tackle intractable problems [7,9,20], and is adopted in this work. Our simulated annealing engine starts with an initial FU binding generated by a force-directed algorithm.…”

Section: Simultaneous Binding and Scheduling For Power Minimizationmentioning

confidence: 99%

“…In [8], a layout-driven high-level synthesis approach was presented to reduce the gap between predicted metrics during RTL synthesis and the actual data after implementation of the FPGA. High-level synthesis for a Multi-FPGA system was done in [9]. The only work we found for low-power high-level synthesis on FPGAs was [10].…”

Section: Introductionmentioning

confidence: 99%

Low-power high-level synthesis for FPGA architectures

Chen¹,

Cong²,

Ye³

2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

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This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estimator closely reflects both dynamic and static power contributed by various FPGA components in 0.1um technology. The power estimation error is 16.2% on average. Second, we present a low power high level synthesis system, named LOPASS, for FPGA designs. It includes two algorithms for power consumption reduction: (i) a simulated annealing engine that carries out resource selection, function unit binding, scheduling, register binding, and data path generation simultaneously to effectively reduce power; (ii) an enhanced weighted bipartite matching algorithm that is able to reduce the total amount of MUX ports by 22.7%. Experimental results show that LOPASS is able to reduce power consumption by 35.8% compared to the results of Synopsys' Behavioral Compiler.

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“…This chapter describes the specification of an application in the RC framework 1 . The specification language used to model an application is very important since it molds the application in a way such that synthesis tools can process it.…”

Section: Rc Architecture Specification Style In Vhdl 21 Introductionmentioning

confidence: 99%

Computer Aided Engineering for Reconfigurable Computing (CAERC)

Vemuri¹

2001

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The public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Department of Defense, Washington Headquarters Services, Directorate for Information Operations and Reports (0704-0188), 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to any penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ADDRESS. REPORT DATE (DD-MM-YY)October 2001 2. REPORT TYPE Approved for public release; distribution unlimited. SUPPLEMENTARY NOTES ABSTRACT (Maximum 200 Words)Synthesis and Partitioning for Adaptive and Reconfigurable Computing Systems (SPARCS) is a computer aided engineering environment for reconfigurable computers. SPARCS contains software implementations of a variety of methods and algorithms for various subproblems for automating the task of producing designs for multi-FPGA (Field Programmable Gate Array) based reconfigurable computers. The SPARCS system includes tools for temporal partitioning, spatial partitioning, high-level synthesis, physical design, and arbiter synthesis. This is a comprehensive report on the SPARCS project, describing various techniques developed for solving these problems. In addition, this report contains some experimental results demonstrating the effectiveness of the SPARCS tools. Reconfigurable processors consisting of a sea of uncommitted FPGAs offer the same performance advantages of custom computing while retaining the flexibility of general purpose instruction architectures. In 1996, at the begining of this project, it was predicted that in near future reconfigurable processors can offer lOOx performance improvement over contemporary microprocessors, and 10-100x reduction in power/gate, 20x progress in density, and l,000,000x reduction in reconfiguration time compared to current reconfigurable devices.Unfortunately, state-of-the-art design synthesis methodologies were able to use perhaps 50-75% of the available gates at 30-50% of the maximum clocking rate of single reprogrammable device and were woefully inadequate in synthesizing multi-device systems. In order to deliver the performance expectations of reconfigurable architectures, dramatic improvements in the synthesis tools were necessary in both directions: (1) ability to synthesize to multiple device architectures, and, (2) improvement in utilization and delivered performance of each device. The goal of this project was to develop a coherent design synthesis and partitioning environment for co...

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An overview of the COBRA-ABS high level synthesis system for multi-FPGA systems

Cited by 19 publications

References 15 publications

LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization

LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization

Low-power high-level synthesis for FPGA architectures

Computer Aided Engineering for Reconfigurable Computing (CAERC)

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