Low-power high-level synthesis for FPGA architectures

Chen, Deming; Cong, Jason; Ye, Fan

doi:10.1145/871540.871541

Cited by 18 publications

(17 citation statements)

References 21 publications

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“…The overall resource usage is therefore simply calculated as the area required for all tasks plus minimum separation from other tasks. We have not at present included a measure for power dissipation, although this can also be a problem, either due to inefficient HDL or use of the FPGA [15]. However, this type of measure could be added to the code relatively simply as part of further work.…”

Section: )mentioning

confidence: 99%

Efficient Task Allocation to FPGAs in the Safety Critical Domain

Conmy

Bate

2011

2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing

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Field Programmable Gate Arrays (FPGAs) are highly configurable programmable logic devices. They offer many benefits over traditional micro-processors such as the ability to efficiently run tasks in parallel and also highly predictable timing performance. They are becoming increasingly popular for use in the safety critical domain where predictability is essential. However, concerns about their dependability, principally their reliability and difficulties in assessing the impact of an internal failure means that current designs are inefficient and conservative. This paper discusses these issues in depth. It also presents an FPGA task allocation method using simulated annealing to balance efficiency and reliability requirements. This can be used to improve designs of safety critical FPGA based systems.

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Section: )mentioning

confidence: 99%

Efficient Task Allocation to FPGAs in the Safety Critical Domain

Conmy

Bate

2011

2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing

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“…Another hardware related issue is the effect that poorly designed VHDL can have on the final performance of the FPGA. For example, power consumption can be significantly impacted [4]. Timing can also be affected by inefficient or poorly thought out code.…”

Section: Design Level Issuesmentioning

confidence: 99%

VHDL guidance for safe and certifiable FPGA design

Conmy¹,

Pygott²,

Bate³

2010

5th IET International Conference on System Safety 2010

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Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular for use within high integrity and safety critical systems. One commonly used coding language for their configuration is the VHSIC Hardware Description Language (VHDL). Whilst VHDL is used for hardware description, it is developed in a similar way to traditional software, and many safety critical software certification standards require the use of coding subsets and style guidance in order to ensure known language vulnerabilities are avoided. At present there is no recognized, public domain guidance for VHDL. This paper draws together many different sources to provide a starting discussion for a VHDL subset.

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“…One of the seminal works for lowpower high-level synthesis used pre-computed tables to characterize RTL and IP block components for power estimation [5]. It was extended to consider the steering logic, such as multiplexers in [6]. The use of a regression tree to improve the power estimation of a RTL component is introduced in [7], in which form a low-level implementation identifies significant variables affecting the power consumption.…”

Section: Previous Workmentioning

confidence: 99%

High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAs

Clover

León

2007

2007 International Conference on Field Programmable Logic and Applications

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We describe the optimization of power consumption obtained by a high level environment developed for the automatic generation of application specific circuits on FPGA. The methodology used is based on the transformation of the whole algorithm in a graph of LUTs that implements all the required operations without the use of library components. The quality of the obtained circuitry is guaranteed by the use of "type inference". Our environment automatically optimizes the word-length and size of operators, and at the same time, reduces the internal data paths and the switching activity. Thus, in the extreme cases tested, the resulting generated circuits offer an important improvement in area usage of up to 95%, and power consumption is reduced by up to 98%.

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Low-power high-level synthesis for FPGA architectures

Cited by 18 publications

References 21 publications

Efficient Task Allocation to FPGAs in the Safety Critical Domain

Efficient Task Allocation to FPGAs in the Safety Critical Domain

VHDL guidance for safe and certifiable FPGA design

High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAs

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