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Abstract-This paper presents the UJI Industrial Robotics Telelaboratory, which lets Ph.D. and Master's degree students perform robotics and computer vision tele-experiments. By using this system, students are able to program experiments remotely via the Web, in order to combine the use of a field-programmable gate array (FPGA) to provide real-time vision processing, a conveyor belt, and a Motoman industrial manipulator. This paper introduces the novel SNRP protocol (i.e., Simple Network Robot Protocol), which permits the integration of network robots and sensors within an e-learning platform in a simple and reliable manner. As long as the students are able to interact remotely with a real robotic scenario, this system helps students very much to learn robotics control techniques like visual servoing control, vision for industrial applications, and robotics manipulation. The various components of the system are connected via a 100BaseT Ethernet network and follow the SNRP protocol, which grants simple access to generic networked devices using enhanced HTTP-based connections. Moreover, the whole telelaboratory is connected to the Internet through a router that permits the user to control the networked devices according to security constraints. The SNRP architecture is compared with a Common Object Request Broker Architecture-based approach, which was used in a previous telelaboratory. This paper describes two principle contributions: the design of a novel SNRP network architecture for the intercommunication of robots and sensors within an e-learning telelaboratory and the integration of a programmable FPGA vision system, which allows students to learn not only robotic techniques but also the design of high-performance circuits for industrial vision applications.
System-on-Chip (SoC) devices can be composed of low-power multicore processors combined with a small graphics accelerator (or GPU) which offers a trade-off between computational capacity and low-power consumption. In this work we use the LLFI-GPU fault injection tool on one of these devices to compare the sensitivity to soft errors of two different CUDA versions of matrix multiplication benchmark. Specifically, we perform fault injection campaigns on a Jetson TK1 development kit, a board equipped with a SoC including an NVIDIA "Kepler" Graphics Processing Unit (GPU). We evaluate the effect of modifying the size of the problem and also the thread-block size on the behaviour of the algorithms. Our results show that the block version of the matrix multiplication benchmark that leverages the shared memory of the GPU is not only faster than the element-wise version, but it is also much more resilient to soft errors. We also use the cuda-gdb debugger to analyze the main causes of the crashes in the code due to soft errors. Our experiments show that most of the errors are due to accesses to invalid positions of the different memories of the GPU, which causes that the block version suffers a higher percentage of this kind of errors.
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