LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization

Abstract

Abstract-In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. LOPASS includes three major components: 1) a flexible high-level power estimator for FPGAs considering the power consumption of various FPGA logic components and interconnects; 2) a simulated-annealing optimization engine that carries out resource selection and allocation, scheduling, functional unit binding, register binding, and interconnection estimation simultaneously to reduce power effectively; and 3) a -cofamily-based register binding algorithm and an efficient port assignment algorithm that reduce interconnections in the data path through multiplexer optimization. The experimental results show that LOPASS produces promising results on latency optimization compared to an academic high-level synthesis tool SPARK. Compared to an early commercial high-level synthesis tool, namely, Synopsys Behavioral Compiler, LOPASS is 61.6% better on power consumption and 10.6% better on clock period on average. Compared to a current commercial tool, namely, Impulse C, LOPASS is 31.1% better on power reduction with an 11.8% penalty on clock period.Index Terms-Behavioral synthesis, field-programmable gate array (FPGA), interconnect, power optimization.

FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation

“…We compare our binding algorithm, HLPower, to a stateof-the-art low-power high-level synthesis algorithm for FPGAs, LOPASS [3] [4], which can perform scheduling, allocation, and binding. We use a resource library containing single-cycle resources, including a multiplier, an adder, a register, and multiplexers.…”

“…In [5], a low-power, simultaneous resource allocation and binding algorithm for FPGAs was presented, and included a high-level power estimator. In [3] and [4], the authors presented a simulated annealing-based algorithm which carried out high-level synthesis subtasks simultaneously, targeting FPGAs for lowpower, called LOPASS. Their binding algorithm initially used minimum weight bipartite matching, and then was enhanced using a network flow approach presented in [2] that binds all the resources simultaneously.…”

FPGA Latency Optimization Using System-level Transformations and DFG Restructuring

“…Perhaps the work most similar to ours is the low-power architectural synthesis system (LOPASS) [7]. This approach performs a simulated-annealing optimization over the entire synthesis process of scheduling, resource selection and allocation, functional unit binding, register binding, and interconnection estimation to effectively reduce power.…”

“…The resource allocation and binding then establishes which operations are performed in which hardware resource, which in turn determines how many registers will be needed to store the partial computations throughout the data flow. The number of multiplexers generated when connecting the registers to and from the operator ports is optimized [7]. These steps are performed in a loop which includes TED restructuring to determine the lowest latency design.…”

Delay modeling of high-speed distributed interconnect for the signal integrity prediction

“…[32][33] based on the use of the negative group delay circuit whose the principle is developed in [34][35] has been introduced. Moreover, accurate, optimized and also easy to implement models enabling the prediction of these unwanted effects are indispensable [36][37][38][39]. In this scope, new generations of design strategies and commercial numerical tools for simulation and characterization of various 3-D structure geometries permitting to ensure the signal fidelity at Gbits/s-speeds were recently reported [40][41][42][43][44].…”