An optically-enabled chip–multiprocessor architecture using a single-level shared optical cache memory

Maniotis, Pavlos; Gitzenis, Savvas; Pleros, Nikos

doi:10.1016/j.osn.2016.05.001

Cited by 10 publications

(11 citation statements)

References 48 publications

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“…The first all-optical cache design was proposed recently in refs. 102,103 , while all its constituent building blocks were demonstrated experimentally [22][23][24][25]104,105 .…”

Section: Cache Memoriesmentioning

confidence: 98%

Optical RAM and integrated optical memories: a survey

2020

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The remarkable achievements in the area of integrated optical memories and optical random access memories (RAMs) together with the rapid adoption of optical interconnects in the Datacom and Computercom industries introduce a new perspective for information storage directly in the optical domain, enabling fast access times, increased bandwidth and transparent cooperation with optical interconnect lines. This article reviews state-of-the-art integrated optical memory technologies and optical RAM cell demonstrations describing the physical mechanisms of several key devices along with their performance metrics in terms of their energy, speed and footprint. Novel applications are outlined, concluding with the scaling challenges to be addressed toward allowing light to serve as both a data-carrying and data-storage medium.

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“…The first all-optical cache design was proposed recently in refs. 102,103 , while all its constituent building blocks were demonstrated experimentally [22][23][24][25]104,105 .…”

Section: Cache Memoriesmentioning

confidence: 98%

Optical RAM and integrated optical memories: a survey

2020

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“…10(b), the shared L1 cache is an optical cache memory technology, connected to CPU and MM via optical waveguides. The direct sharing of the cache among the cores does not necessarily stall the core operation as the optical cache operates at significant higher speeds than the electronic cores, serving concurrently multiple requests from many cores during each electronic core cycle [167]. As can be seen in Fig.…”

Section: From C2c and Rack-scale Disaggregation To Disintegrated mentioning

confidence: 99%

“…Note that optical to electronic conversion is not required at the cache-memory connection as the optical cache memory operates completely in the optical domain. More details about the optical interface technologies that are being considered in the proposed scheme can be found in [167]. The short access time of the optical cache memory layer can theoretically sidestep any bottleneck phenomena arising from the aggregation of the multiple memory requests from the different cores to the single cache.…”

Section: From C2c and Rack-scale Disaggregation To Disintegrated mentioning

confidence: 99%

“…For detailed timing diagrams that present the optical cache circuitry operation at various stages for both Read and Write operations and the TDM-based access scheme followed in the proposed system of Fig. 10 (b), please refer to [164] and [167], respectively.…”

Section: From C2c and Rack-scale Disaggregation To Disintegrated mentioning

confidence: 99%

“…This has been extensively analyzed in [167], where also the performance of the system depicted in Fig.10 was thoroughly investigated via detailed simulations using the gem5 simulation engine and the PARSEC benchmark suite. The main findings when comparing the system of Fig.10(a) with the system of Fig.10(b) for the same amount of total cache capacity can be summarized as follows [167]:  The use of a shared L1 cache yields an important reduction in the cache miss rate of more than 75%, especially when executing parallel programs with high data sharing and exchange needs among their threads; the high volumes of data exchange increase the traffic and consequently the miss rate among the dedicated L1d caches in typical architectures with dedicated L1 caching.  The shared L1 cache negates the need for cache coherency updates and cache coherency protocols, simplifying the program execution and contributing significantly in cache miss ratio reduction by cancelling all cache coherency misses.…”

Section: From C2c and Rack-scale Disaggregation To Disintegrated mentioning

confidence: 99%

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The primary goal of this article is to provide an overview of silicon photonics technology and its applications in the design and improvement of current and future computing systems. We start by reviewing silicon photonics technology and introducing some of its benefits and challenges as well as providing some background on it. Next, we introduce some fundamental silicon photonic components in the design of silicon photonic integrated circuits (PICs) and optical interconnect for computing systems as well as their operating principles and applications. These components can be active, such as photodetectors and optical modulators, or passive, such as silicon‐on‐insulator (SOI) waveguides. Subsequently, we discuss the application of silicon photonics to improve the communication and computation infrastructure in future computing systems, while reviewing the state‐of‐the‐art and some design and implementation challenges. Finally, we discuss several research opportunities to push forward the application of silicon photonics in the design of future computing systems.

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An optically-enabled chip–multiprocessor architecture using a single-level shared optical cache memory

Cited by 10 publications

References 48 publications

Optical RAM and integrated optical memories: a survey

Optical RAM and integrated optical memories: a survey

Optics in Computing: From Photonic Network-on-Chip to Chip-to-Chip Interconnects and Disintegrated Architectures

Silicon Photonics for Future Computing Systems

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