An interval arithmetic-based yield evaluation in circuit tolerance design

Spagnuolo, Giovanni

doi:10.1109/iscas.2002.1009950

Cited by 16 publications

(13 citation statements)

References 7 publications

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“…If the designer uses the central point of the subspace Ω, each adjustment variable can slide around the center without violating any performance or technical constraint. In this way, the size of this subspace is related to the robustness of the circuit [3][4][5][6][7].…”

Section: Solving a Constraint Satisfaction Problemmentioning

confidence: 99%

A robustness-oriented design tool for the topology selection in analog synthesis

Schwartz

Sun

Michel

et al. 2010

2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)

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In order to solve two major bottlenecks of the analog design flow: the time-to-market and the production yield, we introduce in this paper a design tool for measuring the robustness capability of the analog circuit topologies with the guarantee of fulfilling all the design specifications. With this measure, we can describe the feasible subspace by using the set inversion algorithm. A robustness estimation example of a differential pair of a miller CMOS OTA is shown to illustrate this method. I.INTRODUCTION Following the development of analog IC manufacturing and continuous increasing market requirements for a steady improvement in performance, the new analog IC design becomes more and more challenging. Nowadays analog designers have to meet various economical and technical constraints. In this paper, we focus on two dominant constraints: the time-to-market and the production yield. The former requires the enhanced design methodologies and the latter needs to have the robustness introduced in the early stage of the design flow. In a classical design approach, the design process starts with a partitioning of the system. After that, the designer selects an adequate circuit topology and proceeds to carry out the sizing. If the sizing result satisfies the circuit specifications, the designer starts the layout process. Otherwise, the designer must then return to the topology selection. Such iteration can be long and uncertain. Typically, the sizing uses optimization process, which returns a nominal point. The analysis of robustness can be initiated only after the validation of the specifications. Furthermore, the optimization results will find a nominal point in the vicinity of the boundary of the performance space (typically the Pareto front). Our approach introduces a preliminary robustness capability analysis between the topology selection and the nominal sizing process. This analysis can explore several topologies and extract an inner approximation of the feasible subspace for each topology. The measure of this inner approximation size will give a metric to compare the various topologies and focus the nominal sizing process on the most promising circuit in the sense of robustness.

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Section: Solving a Constraint Satisfaction Problemmentioning

confidence: 99%

A robustness-oriented design tool for the topology selection in analog synthesis

Schwartz

Sun

Michel

et al. 2010

2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)

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“…In presence of multivariate function, IA treats the variables as uncorrelated. In presence of parameters variations, IA permits a straight determination of an interval that certainly includes the range of a function, thanks to the "monotonic inclusion property" (Moore, 1966) and it can be suitably adopted in a worst-case design (Spagnuolo, 2002).…”

Section: Performance Function Robustness and Interval Analysismentioning

confidence: 99%

Interval approach to robust design

Lamberti

Tucci

2007

COMPEL - The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

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Purpose -Aims to present a novel approach for the worst-case, robust design (RD) of an electromagnetic system able to overcome some discretionary aspects of the available methods. Design/methodology/approach -The proposed methodology is based on a suitable application of the interval arithmetic and considers the width of the interval Taylor extension (WITE) of the performance function (PF) as a valuable robustness index (RI). In particular, the most robust stationary point is obtained by looking for the minimum of a continuous, non-differentiable function thanks to the properties of WITE. Findings -The method furnishes a reliable classification of the robust solutions with PFs expressed by either mono or multi-dimensional polynomial forms and provides the over-bounding of the PF without additional computational efforts. Research limitations/implications -Limitations concern the necessity of an analytic formulation of the system performance. The IA approach may lead to lose some robust solution. Practical implications -A RI can be assigned in analytic form and it can be suitably used as a figure of merit in a multi-objective optimisation problem. Originality/value -The use of the interval analysis for the worst-case, RD of an electromagnetic system is original. The system designer may find the most robust stationary solution by means of a continuous, non-differentiable function.

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“…In the following, we will just stress some crucial aspects of interest to the IA-based approach to yield evaluation. A more detailed discussion of the IA-based algorithm, instead can be found in [2], with an application to a circuit characterized by a non convex and non simply connected ROA.…”

Section: B the Interval Arithmetic-based Approachmentioning

confidence: 99%

“…The main features of the proposed method are reliability and robustness, which often are leading aspects with respect to computation speed. As shown in [2], the IA-based approach overcomes the limits of other techniques that suffer from "black holes" of unfeasibility in the TR and/or assume a simply connected and convex ROA. The examples presented in Section I11 show its features.…”

Section: Unfeasibility Test (Uft): If Exists At Least One K L~~mentioning

confidence: 99%

“…This unwelcome circumstance makes the tolerance design process more difficult and dependent on the degrees of non-linearity and non-monotonicity of the design constraints. In some casesnot simply predictable -the ROA does not exhibit neither convexity nor simple connection [1] [2]. Such cases may occur also in linear circuits with few parameters, as the ROA's shape depends on the type of relations expressing the constraints as functions of parameters.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Reliable worst-case tolerance design of feedback regulated DC-DC converters by evolutionary algorithms and interval arithmetic

Femia

Spagnuolo

2002 IEEE 33rd Annual IEEE Power Electronics Specialists Conference. Proceedings (Cat. No.02CH37289)

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In this paper a reliable approach to the tolerance design of electronic circuits is presented. Firstly, the tolerances of parameters are maximized by means of an evolutionary algorithm according to the design constraints. This optimization step is based on vertex analysis: each candidate solution is considered as feasible if the design constraints are fulfilled in all of the vertices of the tolerance region corresponding to that solution. This approach ensures fast computation and good results provided that the region of acceptability is convex and simply connected. Otherwise, the actual feasibility of the designed tolerance region is verified. To this purpose, a recursive divide-and-conquer algorithm based on interval arithmetic is used. It allows detecting possible infeasibility pockets included in the designed tolerance region and neglected during the optimization step. Any portion of the boundaries of the region of acceptability that is included in the tolerance region is identified and the analysis is refined across it. The technique proposed in the paper has been applied to the tolerance design of two different possible realizations of the feedback control network of a voltage-mode regulated DC-DC converter. The results show that the method guarantees a considerable enlargement of the parameters' tolerances up to the boundary of the region of acceptability. Moreover, a reliable and efficient validation of the designed tolerance region is performed even in presence of nonconvex and not simply connected region of acceptability

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An interval arithmetic-based yield evaluation in circuit tolerance design

Cited by 16 publications

References 7 publications

A robustness-oriented design tool for the topology selection in analog synthesis

A robustness-oriented design tool for the topology selection in analog synthesis

Interval approach to robust design

Reliable worst-case tolerance design of feedback regulated DC-DC converters by evolutionary algorithms and interval arithmetic

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