A robustness-oriented design tool for the topology selection in analog synthesis

Abstract

In order to solve two major bottlenecks of the analog design flow: the time-to-market and the production yield, we introduce in this paper a design tool for measuring the robustness capability of the analog circuit topologies with the guarantee of fulfilling all the design specifications. With this measure, we can describe the feasible subspace by using the set inversion algorithm. A robustness estimation example of a differential pair of a miller CMOS OTA is shown to illustrate this method. I.INTRODUCTION Following the development of analog IC manufacturing and continuous increasing market requirements for a steady improvement in performance, the new analog IC design becomes more and more challenging. Nowadays analog designers have to meet various economical and technical constraints. In this paper, we focus on two dominant constraints: the time-to-market and the production yield. The former requires the enhanced design methodologies and the latter needs to have the robustness introduced in the early stage of the design flow. In a classical design approach, the design process starts with a partitioning of the system. After that, the designer selects an adequate circuit topology and proceeds to carry out the sizing. If the sizing result satisfies the circuit specifications, the designer starts the layout process. Otherwise, the designer must then return to the topology selection. Such iteration can be long and uncertain. Typically, the sizing uses optimization process, which returns a nominal point. The analysis of robustness can be initiated only after the validation of the specifications. Furthermore, the optimization results will find a nominal point in the vicinity of the boundary of the performance space (typically the Pareto front). Our approach introduces a preliminary robustness capability analysis between the topology selection and the nominal sizing process. This analysis can explore several topologies and extract an inner approximation of the feasible subspace for each topology. The measure of this inner approximation size will give a metric to compare the various topologies and focus the nominal sizing process on the most promising circuit in the sense of robustness.