An Easily Testable Routing Architecture and Prototype Chip

Abstract

SUMMARYGenerally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. The first is that an automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The base of our architecture is general island-style FPGA architecture, but it consists of a few types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We evaluated our architecture and test configurations using a prototype chip. As a result, the chip was fully tested using our configurations in a short test time. Moreover, our architecture can provide comparable performance to a conventional FPGA architecture. key words: design for testability, homogeneous architecture, test method, prototype chip

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core

“…In addition, we discuss fault diagnostics time, recovery time, and circuit performance for an FPGA-IP core loaded on the system LSI. Fault diagnostics are performed using additional test patterns based on our previously proposed method [16]. Furthermore, for fault recovery, we have developed a tool at the tile and MUX levels; our tool is an improvement over the University of Toronto's VPR [17].…”

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC

“…2). Since island-style FPGAs can have various tile topologies [14], configuration data is not the same for each logic tile. As a result, configuration data cannot be simply moved from faulty tiles to spare tiles.…”

“…As a result, configuration data cannot be simply moved from faulty tiles to spare tiles. Thus, [14] proposed a uniform tile structure referred to as homogeneous FPGA. Also, fault detection techniques using the SB topology have been proposed [8] that allow detection of the locations of any faults in FPGA cores (see the next subsection for details on these methods).…”

“…Thus, automatic test pattern generation tools for ASICs cannot be used directly for FP-GAs. To address this problem, we proposed a simple and regular FPGA structure [14] suitable for design for test (Fig. 2).…”

“…5). FT-FPGA is based on the homogeneous routing architecture in [14], which has a simple regular structure. To implement physical fault avoidance, spare tiles are introduced to the homogeneous FPGA.…”