Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core

Abstract

SUMMARYFault tolerance is an important feature for the system LSIs used in reliability-critical systems. Although redundancy techniques are generally used to provide fault tolerance, these techniques have significantly hardware costs. However, FPGAs can easily provide high reliability due to their reconfiguration ability. Even if faults occur, the implemented circuit can perform correctly by reconfiguring to a fault-free region of the FPGA. In this paper, we examine an FPGA-IP core loaded in SoC and introduce a fault-tolerant technology based on fault detection and recovery as a CAD-level approach. To detect fault position, we add a route to the manufacturing test method proposed in earlier research and identify fault areas. Furthermore, we perform fault recovery at the logic tile and multiplexer levels using reconfiguration. The evaluation results for the FPGA-IP core loaded in the system LSI demonstrate that it was able to completely identify and avoid fault areas relative to the faults in the routing area.

An eFPGA Generation Suite with Customizable Architecture and IDE

“…In addition, the routing part of an FPGA involves a huge number of switch combinations, which makes it difficult to implement the test circuit. In our eFPGA suite, we adopt a previously developed FPGA test method in reference [16] for stuck-at faults in logics and routing resources.…”

“…Our eFPGA generation suite has the full support of the shipping test. We adopt an easy-to-test FPGA architecture and a test method proposed in previous research [16], however, the test method only supported wiring resources. A homogeneous architecture that unifies the structure of all logic tiles is used to simplify testing.…”