Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC

Abstract

SUMMARYIn this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their design framework for intellectual property (IP) cores in system-on-chip (SoC). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are a regular tile structure, spare modules and bypass wires for fault avoidance, and a configuration mechanism for singlecycle reconfiguration. In addition, we utilize routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGAs and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 1.82 times the area and 1.11 times the delay compared with traditional island-style FPGAs. At the same time, our FPGA shows a higher fault tolerant performance.

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core

“…The feature of the architecture is summarized in this section. More detail information and evaluation results can be obtained in [2].…”

“…Note that we utilize scan type FFs as a configuration memory cells. Figure 21 (b) shows the layout of the tile array; its area is 0.34 mm 2 . Figures 21 (c) and (d) shows the layout of normal and spare tiles.…”

“…After we mainly describe detail of CAD-based approach, hardware-based one is introduced based on [2]. The remainder of the present paper is organized as follows.…”