An asymmetric sidewall process for high performance LDD MOSFET's

Horiuchi, T.; Homma, Tetsuya; Murao, Y.; Okumura, K.

doi:10.1109/16.277381

Cited by 35 publications

(21 citation statements)

References 8 publications

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“…ADSG FinFETs require an extra mask to dope the source and drain unequally [Moradi et al 2011]. AUSG FinFETs also require an extra mask to create an asymmetric underlap, which can be achieved using an asymmetric sidewall spacer [Horiuchi et al 1994] or tilt ion implantation [Ghani et al 2001]. The first step of asymmetric sidewall spacer technique is photo masking of the drain side of the FinFET, which requires a precise alignment of the mask to the gate.…”

Section: Discussionmentioning

confidence: 99%

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Guler

Jha

2016

J. Emerg. Technol. Comput. Syst.

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Memory arrays consisting of Static Random Access Memory (SRAM) cells occupy the largest area on chip and are responsible for significant leakage power consumption in modern microprocessors. With the transition from planar Complementary Metal-Oxide-Semiconductor (CMOS) technology to FinFETs, FinFET SRAM design has become important. However, increasing leakage power consumption of FinFETs due to aggressive scaling, width quantization, read-write conflict, and process variations make FinFET SRAM design challenging. In this article, we show how Multiparameter Asymmetric (MPA) FinFETs can be used to design ultra-low-leakage and robust 6T SRAM cells. We combine multiple asymmetries, namely, asymmetry in gate work function, source/drain doping concentration, and gate underlap, to address various SRAM design issues all at once. We propose five novel MPA FinFET SRAM cell designs and compare them with symmetric and Single-Parameter Asymmetric (SPA) FinFET SRAM cells using dc and transient metrics. We show that the leakage current of MPA FinFET SRAM cells can be reduced by up to 58× while ensuring reasonable read/write stability metric values. In addition, high stability metric values can be achieved with 22× leakage current reduction compared to the traditional symmetric FinFET SRAM cell. There is no area overhead associated with MPA FinFET SRAM cells. ACM Reference Format:Abdullah Guler and Niraj K. Jha. 2016. Ultra-low-leakage, robust FinFET SRAM design using multiparameter asymmetric FinFETs.

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Section: Discussionmentioning

confidence: 99%

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Guler

Jha

2016

J. Emerg. Technol. Comput. Syst.

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“…In order to realize devices with asymmetric SDE regions, technique such as asymmetric sidewall spacer technology [28] could be used. The first step of the proposed process could be the photo masking and a window pattern at the drain side of the device.…”

Section: Device Design and Optimizationmentioning

confidence: 99%

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

Kranti

Armstrong

2007

Microelectronic Engineering

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“…Prior to the source / drain doping, spacers are etched asymmetrically on the two opposite sides of the gate [15,16]. Similar process can be used to fabricate asymmetrically gate-underlapped FinFETs.…”

Section: Hybrid Finfet Sram Cell With Asymmetrically Gate-underlap Enmentioning

confidence: 99%

“…Fabrication of asymmetrically gate-underlapped single gate MOSFETs are reported in [15] and [16] by Advanced Micro Devices (AMD) Incorporation and NEC Corporation, respectively. Prior to the source / drain doping, spacers are etched asymmetrically on the two opposite sides of the gate [15,16].…”

Section: Hybrid Finfet Sram Cell With Asymmetrically Gate-underlap Enmentioning

confidence: 99%

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

Salahuddin

Kursun

Jiao³

2015

Transactions on Electrical and Electronic Materials

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Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology. Keywords

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An asymmetric sidewall process for high performance LDD MOSFET's

Cited by 35 publications

References 8 publications

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

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