An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applications

Maricau, Elie; Wit, Pieter De; Gielen, Georges

doi:10.1016/j.microrel.2008.06.016

Cited by 35 publications

(21 citation statements)

References 3 publications

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“…In our earlier work, we found a current flow caused by impact ionization at large drain biases [4]. High energy channel electrons and possibly secondary electrons created by impact ionization are injected at the drain side [16] and cause the positive V th shift. Also, the high-κ quality/thickness towards the drain contact is essential for HCI reliability.…”

Section: Resultsmentioning

confidence: 87%

RF and DC Analysis of Stressed InGaAs MOSFETs

Roll

Lind

Egard

et al. 2014

IEEE Electron Device Lett.

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Abstract-A complete reliability study of the DC and RF characteristics for InGaAs nMOSFETs with Al2O3/HfO2 dielectric is presented. The main stress variation at high frequencies is related to a threshold voltage shift, whereas no decrease is found in the maximum of the cut-off frequency and RF-transconductance. Constant gate stress leads to a charge build up within the gate oxide causing a threshold voltage shift. Furthermore, electron trapping at the drain side degrades the performance after hot carrier stress. The maximum DC-transconductance is reduced following constant gate bias stress, by an increase in charge trapping at border defects. These border defects at the channel/high-κ interface are filled by cold carrier trapping when the transistor is turned on, whereas they do not respond at high frequencies.

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Section: Resultsmentioning

confidence: 87%

RF and DC Analysis of Stressed InGaAs MOSFETs

Roll

Lind

Egard

et al. 2014

IEEE Electron Device Lett.

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“…The degradation models for both HC and NBTI used in the simulator are verified and characterized through measurements on single devices [9], [6]. The example is simulated in a 90nm technology.…”

Section: Resultsmentioning

confidence: 99%

“…where σ 2 (∆V T H ) is given by equation (3) and σ 2 (∆β) can be derived from (3) using [6]. Equation (9), however, provides little or no insight in the effect of process variability on the degradation of the circuit specifications.…”

Section: Resultsmentioning

confidence: 99%

“…the threshold voltage V T H , the carrier mobility β and the output conductance g o ). However, since expressions for all degrading transistor parameters can be derived from the threshold voltage V T H [6], we will continue to work with V T H from here on. The time-dependent behavior of V T H can, for both HC and NBTI, be described as a powerlaw function of time [7]:…”

Section: Degradation Modelsmentioning

confidence: 99%

“…V DS , T , L, ...) and is different for either degradation phenomenon. We already presented a HC degradation model in previous work [6]. For NBTI, values for the process-related parameters in equation (4) are extracted from measurement results in [9].…”

Section: Degradation Modelsmentioning

confidence: 99%

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Efficient reliability simulation of analog ICs including variability and time-varying stress

Maricau

Gielen

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Aggressive scaling to nanometer CMOS technologies causes both analog and digital circuit parameters to degrade over time due to die-level stress effects (i.e. NBTI, HCI, TDDB, etc). In addition, failure-time dispersion increases due to increasing process variability. In this paper an innovative methodology to simulate analog circuit reliability is presented. Advantages over current state of the art reliability simulators include, among others, the possibility to estimate the impact of variability and the ability to account for the effects of complex time-varying stress signals. Results show that taking time-varying stress signals into account provides circuit reliability information not visible with classic DC-only reliability simulators. Also, variability-aware reliability simulation results indicate a significant percentage of early circuit failures compared to failure-time results based on nominal design only.

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