Efficient reliability simulation of analog ICs including variability and time-varying stress

Maricau,; Gielen,

doi:10.1109/date.2009.5090853

Cited by 23 publications

(10 citation statements)

References 8 publications

(14 reference statements)

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“…This implies that the above reliability analysis must be repeated for a large number of statistical circuit instances. A crude approach is to solve this with MonteCarlo analysis [20]. However, to avoid the time-consuming Monte-Carlo analysis, a more efficient variability-aware reliability analysis is presented in [21] and shown in Fig.…”

Section: Reliability Analysis Of Analog Integrated Circuitsmentioning

confidence: 99%

“…In [20] a novel and very efficient method for reliability simulation is presented, offering more correct results than commercial tools. It uses a short transient simulation that provides accurate information about the stress at every circuit node, while a degradation extrapolation ensures a fast simulation result.…”

Section: Reliability Analysis Of Analog Integrated Circuitsmentioning

confidence: 99%

See 1 more Smart Citation

Design automation towards reliable analog integrated circuits

Gielen¹,

Maricau²,

Wit³

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Reliability is becoming one of the major concerns in designing integrated circuits in nanometer CMOS technologies. Problems related to degradation mechanisms like NBTI or soft breakdown, as well as increased external interference such as caused by crosstalk and EMI, cause timedependent circuit performance degradation. Variability only makes these things more severe. This creates a need for innovative design techniques and design tools that help designers coping with these reliability and variability problems. This tutorial paper gives a brief description of design tools for the efficient analysis and identification of reliability problems in analog circuits, as a first step towards the automated design of guaranteed reliable analog circuits.

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Section: Reliability Analysis Of Analog Integrated Circuitsmentioning

confidence: 99%

Section: Reliability Analysis Of Analog Integrated Circuitsmentioning

confidence: 99%

Design automation towards reliable analog integrated circuits

Gielen¹,

Maricau²,

Wit³

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…To cope with these issues reliability simulators, capable of detecting reliability problems in both analog and digital circuits, need to be developed. In literature, different simulator methodologies have been proposed [4], [6], [7], [8]. For digital circuit simulation, DC only simulations provide a good insight in the behavior of a circuit over time.…”

Section: Degradation Models For Circuit Simulationmentioning

confidence: 99%

“…To obtain this result, a carefull study of different measurement and modelling problems, associated with the most important degradation phenomena, was performed. The workflow intends to be a useful tool to get a first order estimate of the impact of degradation on digital and analog circuits [4]. As such it is complementary to existing measurement techniques intended to understand the physical nature of different degradation effects [3], [5].…”

Section: Introductionmentioning

confidence: 99%

A methodology for measuring transistor ageing effects towards accurate reliability simulation

Maricau

Gielen

2009

2009 15th IEEE International on-Line Testing Symposium

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Abstract-Emerging die-level stress effects (i.e. NBTI, HCI, TDDB, etc.) in nanometer CMOS technologies cause both analog and digital circuit parameters to degrade over time. To efficiently evaluate these degradation effects in modern ICs, a reliability simulator, using accurate first order degradation models, is needed. In this work, we propose a new measurement workflow addressing several modelling and measurement issues involved with developing these new degradation models. A new on-the-fly measurement technique, avoiding complicated NBTI relaxation problems, is introduced. This technique provides a complete set of easy-to-use modelling parameters and allows the modelling of both DC and AC stress effects in all transistor operating regions. To eliminate large extrapolation errors, we also propose a simple measurement circuit suited for fast and accurate degradation modelling at nominal voltages and temperatures. Avoiding the use of complicated and technology restricted transistor models, this new methodology is very flexible and can be used over a broad range of nanometer CMOS processes.

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“…All of those methods rely on the analytical expression of performance features, which is suitable for digital circuits but difficult in analog domain. For analog circuits, authors in (Maricau & Gielen, 2009) use Monte-Carlo simulation loop to obtain the degraded performance values for each fresh random sample at every lifetime point. Then the most appropriate distribution function at each time is fitted, thus a failure distribution throughout the lifetime can be found.…”

Section: State Of the Artmentioning

confidence: 99%