2009 15th IEEE International on-Line Testing Symposium 2009
DOI: 10.1109/iolts.2009.5195978
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A methodology for measuring transistor ageing effects towards accurate reliability simulation

Abstract: Abstract-Emerging die-level stress effects (i.e. NBTI, HCI, TDDB, etc.) in nanometer CMOS technologies cause both analog and digital circuit parameters to degrade over time. To efficiently evaluate these degradation effects in modern ICs, a reliability simulator, using accurate first order degradation models, is needed. In this work, we propose a new measurement workflow addressing several modelling and measurement issues involved with developing these new degradation models. A new on-the-fly measurement techn… Show more

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Cited by 2 publications
(2 citation statements)
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“…There is a clear understanding of the underlying degradation process. There exists vast literature such as: fatigue models for modelling initiation and propagation of cracks in structural components [25], electrolytic overstress ageing [26], Arrhenius equation for prediction of resistance drift [27], physics inspired power model [28] or log-linear model for degradation of current drain [29], physics-inspired exponential degradation model for aluminum electrolytic capacitors [30] etc. Given the behavioral model of damage progression, the current SOH is popularly obtained in probabilistic domain with the help of Bayesian estimation techniques.…”
Section: Data Driven Prognosticsmentioning
confidence: 99%
“…There is a clear understanding of the underlying degradation process. There exists vast literature such as: fatigue models for modelling initiation and propagation of cracks in structural components [25], electrolytic overstress ageing [26], Arrhenius equation for prediction of resistance drift [27], physics inspired power model [28] or log-linear model for degradation of current drain [29], physics-inspired exponential degradation model for aluminum electrolytic capacitors [30] etc. Given the behavioral model of damage progression, the current SOH is popularly obtained in probabilistic domain with the help of Bayesian estimation techniques.…”
Section: Data Driven Prognosticsmentioning
confidence: 99%
“…NBTI and HCI are dominant wearout effects and have thus been more intensively studied [27]. Conventionally, aging effects are studied under DC stress conditions where it is easier to measure transistor parameters [18,22,25]. However, AC stress conditions are more realistic for high-frequency long-term CMOS operation; hence works such as those of [19,36,27] discuss such long-term models, while other works introduce the relationship between DC and AC stress conditions [37].…”
Section: Related Workmentioning
confidence: 99%