An analysis of the reliability of a wafer level package (WLP) using a silicone under the bump (SUB) configuration

González, Mario; Vandevelde, Bart; BuIcke, M.V.; Winters, C.; Beyne, Eric; Lee, Y.I.; Larson, Lyndon; Harkness, Brian R.; Mohamed, Mazlan; Meynen, H.; Vanlathem, Eric

doi:10.1109/ectc.2003.1216391

Cited by 10 publications

(8 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A new class of silicone materials has recently been introduced, which has considerably, lower residual tensile stress [2]. These low modulus, highly flexible patternable silicone materials are able to absorb deformations and reduce stresses created in the device by the coefficient of thermal expansion (CTE) mismatches of different materials [3]. The intrinsically low stres-0167-9317/$ -see front matter Ó 2004 Elsevier B.V. All rights reserved.…”

Section: Introductionmentioning

confidence: 99%

Ultra low stress and low temperature patternable silicone materials for applications within microelectronics

Meynen¹,

Bulcke

González

et al. 2004

Microelectronic Engineering

Self Cite

View full text Add to dashboard Cite

Section: Introductionmentioning

confidence: 99%

Ultra low stress and low temperature patternable silicone materials for applications within microelectronics

Meynen¹,

Bulcke

González

et al. 2004

Microelectronic Engineering

Self Cite

View full text Add to dashboard Cite

“…The relationship between the pad size of the solder ball after mounting on the substrate and itself reliability is explored in many technical literatures. In spite of the discrepancy in the packaging structure, such as the ball grid array (BGA) and the UltraCSP WLP [9], the analytical results nevertheless indicate that the reliability will be enhanced if the size of the upper part of the pad of the solder joint was slightly larger than the bottom part of the pad [4], [5]. Chiang a WLP, and employed the finite element analysis (FEA) to optimize the built-in stress-relaxation layer for reducing the strain of the solder bumps [7].…”

Section: Introductionmentioning

confidence: 99%

“…Hedler et al applied the elastomeric bump technology to enrich the interconnect reliability of WLP [8]. In addition, Gonzalez et al [9] introduced the concept of silicone under the bump (SUB) thereby creating the mechanical property of low module within the WLCSP so as to release the thermal stresses.…”

Section: Introductionmentioning

confidence: 99%

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

Lee

Liu²,

Chiang³

2007

IEEE Trans. Comp. Packag. Technol.

View full text Add to dashboard Cite

With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP) [1] with a stress buffer layer and bubble-like plate (Fig. 1) are proposed in this research to improve the solder joint fatigue life. The thermal stress caused by the coefficient of thermal expansion mismatch can be significantly reduced, and the reliability of the WLP could be substantially enhanced by this new design. In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYS is utilized. In additions, the methodology based on the finite element method (FEM) used in the study has been verified by the relative experiments in our previous researches. The design parameters include the thickness of the stress buffer layer, thickness, bending angle and standoff height of the different types of bubble-like plate. The results of the FEM analysis reveal that the stress buffer layer and bubble-like plate can relax the thermal stresses of solder joints and enhance the package reliability. Besides, the peeling stress between stress buffer layer and two different types of bubble-like plates is discussed, and the stress state of the leadframe is also analyzed in this research. Furthermore, the findings of this research can be used as the guideline for advanced WLCSP design.Index Terms-Bubble-like stress buffer layer, chip scale packages (CSP), finite element method (FEM), reliability, simulation, wafer level packages (WLP).

show abstract

“…Although Finite Element predictions cannot substitute entirely the thermo-mechanical testing, it can be used as a guideline to reduce the number of prototypes necessary to screen for the best design and materials for a specific package layout [7]. In choosing the materials for such a design, specific consideration has been given in this case to silicones, as they have already been shown to enhance solder joint reliability for chip scale packages [81.…”

Section: Introductionmentioning

confidence: 99%

Finite element analysis of an improved wafer level package using silicone under bump (SUB) layers

González

Bulcke

Vandevelde

et al.

5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, 2004. E

Self Cite

View full text Add to dashboard Cite

The low fatigue resistance of solder joints limits the reliability of many types of electronic packages. In this study, the reliability of a Wafer Level Package (WLP) was optimized by introducing a flexible silicone bump between the solder joint and the chip in order to buffer the strains and stresses in the solder during thermal cycling. Silicones are non-conductive materials and therefore a metal layer must be applied over the silicone bump for electrical conductivity. The reliability of the package was optimized by balancing the reliability of the solder joint with that of the metallization. The thermomechanical behavior of the eutectic SnPb solder joints and copper metallization was analyzed using a non-linear 3D Finite Element Model (FEM) and accelerated thermal test cycles. Failure analysis after traditional reliability tests of an actual wafer level package shows good agreement with FEM predictions.

show abstract

An analysis of the reliability of a wafer level package (WLP) using a silicone under the bump (SUB) configuration

Cited by 10 publications

References 8 publications

Ultra low stress and low temperature patternable silicone materials for applications within microelectronics

Ultra low stress and low temperature patternable silicone materials for applications within microelectronics

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

Finite element analysis of an improved wafer level package using silicone under bump (SUB) layers

Contact Info

Product

Resources

About