In this work, the design of flexible and stretchable interconnections is presented. These interconnections are done by embedding sinuous electroplated metallic wires in a stretchable substrate material. A silicone material was chosen as substrate because of its low stiffness and high elongation before break. Common metal conductors used in the electronic industry have very limited elastic ranges; therefore a metallization design is crucial to allow stretchability of the conductors going up to 100%.Different configurations were simulated and compared among them and based on these results, a horseshoe like shape was suggested. This design allows a large deformation with the minimum stress concentration. Moreover, the damage in the metal is significantly reduced by applying narrow metallization schemes. In this way, each conductor track has been split in four parallel lines of 15 ptm and 15 ptm space in order to improve the mechanical performance without limiting the electrical characteristics. Compared with the single copper or gold trace, the calculated stress was reduced up to 10 times.
This paper describes a novel Wafer Level Package using a Silicone Under the Bump (SUB) design.The SUB architecture is designed to access the elastomeric qualities of silicones to reduce stresses on solder joints in a chip scale package. Poor reliability of the solder joints frequently arises from stresses generated by the mismatch in coefficient of thermal expansion between the die and the printed circuit board (PCB). Integration of a low modulus silicone pad between the die and solder ball allows for additional deformation mechanisms to dissipate stress between the die and the PCB during thermal cycling, increasing device reliability.Key to the realization of a SUB device was the integration of an elastomeric pad using the recently commercialized Dow Corning@ WL-5 150 Photodefinable Spin-on Silicone. SUB devices containing 40 pm thick silicone pads were successfully built using a series of standard processing steps including photolithography, plasma cleaning, and metallization. Two different SUB solder joint designs, suggested by finite element analysis, were constructed and evaluated under thermal cycling. Failure mechanisms in the devices were determined to be dependent on the metallization scheme for the electronic connections. Incorporation of the silicone pads in a SUB device resulted in a 90% increase in reliability relative to control devices without the silicone pad. The failure mechanisms observed suggested an intermediate metallization approach to m h e r enhance reliability.
Microelectronics devices continue to evolve towards increased functionality, thinner die, increased reliability, and reduced cost, requiring a change in material and process requirements for the next generation of packages (i.e. stacked chip packages and wafer level packages (WLP)). Stress reduction is a key factor for many devices, particularly those that have thinner die and those that are subjected to stresses generated by thermal cycling. Wafer level packaging is an area where low stress and high volume manufacturing are critical for achieving good reliability and low manufacturing cost. Dow Coming and IMEC have been investigating a Silicone Under the Bump (SUB) wafer level package as a potential route towards increased reliability. Including a SUB design into the device architecture provides a route to dissipate the stresses generated by the thermal expansion mismatch between the silicon die and the printed circuit board. Key to the device build is the application of a silicone pad using a photosensitive silicone or a screen printable silicone. In the design, metal traces from the bonding pads are redistributed to the tops of the silicone pads. Solder balls are placed on the metallized pads to complete the interconnection. The elastomeric nature of the pad dissipates the stresses created by the mismatch in CTE between the chip and the PCB and extends device reliability.To build the SUB enabled WLP device it was critical to understand the impact of the new materials on the device process steps. The uniqueness of the material set requires the creation and optimization of plasma cleaning processes specific to silicones, direct-on-silicone metallization and metal etching in the presence of silicones. The application of a solder mask and solder ball placement is required to complete a successful device build.In this paper we will discuss in detail the process steps utilized in building a silicone containing WLP. This will include a discussion on the process challenges including silicone pad integration, metallization, solder mask application and solder ball placement. The methodologies described in this paper can be generally applied for integration of photopatternable silicones into a range of devices and packages.
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