Finite element analysis of an improved wafer level package using silicone under bump (SUB) layers

Abstract

The low fatigue resistance of solder joints limits the reliability of many types of electronic packages. In this study, the reliability of a Wafer Level Package (WLP) was optimized by introducing a flexible silicone bump between the solder joint and the chip in order to buffer the strains and stresses in the solder during thermal cycling. Silicones are non-conductive materials and therefore a metal layer must be applied over the silicone bump for electrical conductivity. The reliability of the package was optimized by balancing the reliability of the solder joint with that of the metallization. The thermomechanical behavior of the eutectic SnPb solder joints and copper metallization was analyzed using a non-linear 3D Finite Element Model (FEM) and accelerated thermal test cycles. Failure analysis after traditional reliability tests of an actual wafer level package shows good agreement with FEM predictions.

Reliability Analysis of a New Soft Joint Protection Technology Using in WLCSP

“…The development of new electronic packages has focused on low cost, small size and more reliable components [1][2][3]. The WLCSP technology completes the packaging operation directly on the wafer with the chip scaled size, and so has a high potential for future electronic packaging.…”

“…However, the reliability of the large chip size and the cost increase for the additional manufacturing processes remain questionable. One of the improvements to the WLCSP is the soft stress-buffer-layer (SBL) structure which is formed under the solder bumps to release the shear stress in the solder joints [2,4,5]. This thick SBL coated on the die side can increase packaging reliability, but the manufacturing process is difficult.…”