Reliability Analysis of a New Soft Joint Protection Technology Using in WLCSP

Abstract

The coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB) causes a reliability issue for the ball grid array type electronic package. This makes it difficult for the conventional wafer level chip scaled packaging (WLCSP) with large die to satisfy the reliability requirement. Therefore, in this study a novel solder joint protection -WLCSP (SJP -WLCSP) structure is proposed to overcome the reliability issue. The SJP-WLCSP makes use of a delaminating layer to reduce the problem of CTE mismatch. In the SJP-WLCSP, a delaminating layer is interposed between the top layer of the chip and the bottom insulating layer of the redistribution copper metal traces. As a result, the stress on the solder joints can be released by allowing cracks to form in the delaminating layer. To elucidate the thermo-mechanical behavior of eutectic solder joints and copper trace, a nonlinear analysis based on the 3D finite element (FE) model under accelerated thermal test loadings was carried out. The crack of the SJP-WLCSP test vehicle after thermal cycling loadings exhibits a good agreement between the failure analysis experiments and the FE method predictions.

Board level WLCSP 3D thermal stress analysis by submodeling of FEA

“…This makes it difficult for the conventional wafer level chip scaled packaging with large die to satisfy the reliability requirement [3]. Besides, the WLCSP is typically used without underfill, the solder joints have to carry the entire load.…”