3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

Abstract

With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP) [1] with a stress buffer layer and bubble-like plate (Fig. 1) are proposed in this research to improve the solder joint fatigue life. The thermal stress caused by the coefficient of thermal expansion mismatch can be significantly reduced, and the reliability of the WLP could be substantially enhanced by this new design. In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYS is utilized. In additions, the methodology based on the finite element method (FEM) used in the study has been verified by the relative experiments in our previous researches. The design parameters include the thickness of the stress buffer layer, thickness, bending angle and standoff height of the different types of bubble-like plate. The results of the FEM analysis reveal that the stress buffer layer and bubble-like plate can relax the thermal stresses of solder joints and enhance the package reliability. Besides, the peeling stress between stress buffer layer and two different types of bubble-like plates is discussed, and the stress state of the leadframe is also analyzed in this research. Furthermore, the findings of this research can be used as the guideline for advanced WLCSP design.Index Terms-Bubble-like stress buffer layer, chip scale packages (CSP), finite element method (FEM), reliability, simulation, wafer level packages (WLP).

Towards Alleviating Counterproductive Work Behaviour: A Soul Leadership View

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“…Cronbach's alphas and composite reliability coefficients were computed which was found to be acceptable, i.e., greater than 0.60 (Tang, 2008) and 0.70 (Lee, Liu & Chiang, 2007) respectively. Also, convergent and discriminant validities were also computed to confirm the constructs' validity.…”

Board level temperature cycling study of large array Wafer Level Package

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“…Driel et al [1] published results on 1 st and 2 nd level reliability of WLP using combined experimental and virtual prototyping (thermal, mechanical and thermo-mechanical) techniques. Novel wafer-level chip scale packages (WLCSP) with a stress buffer layer and bubble-like plate were proposed to improve the solder joint fatigue life by Lee et al [2]. Zbrzezny el at.…”

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“…To resolve the reliability problems produced by the CTE mismatch between the chip and the organic substrate, many improvements have been and are continuously being developed. One of the general improvements of the WLP is the soft stress buffer layer (SBL) structure, which is normally formed under the solder bumps to release the stresses in the solder joints (Badihi, 2000; Dudek et al , 2006; Gonzalez et al , 2003; Lee et al , 2007). In these proposals, the soft and polymer‐like materials which have large CTEs are utilized as the SBL.…”