Board level temperature cycling study of large array Wafer Level Package

Abstract

The demand for Wafer Level Packages (WLP) has increased significantly due to its smaller package size and lower cost. However, board level reliability of WLP is still a major concern. This study investigates the board level temperature cycle reliability of three very different wafer level package configurations. Comprehensive studies are carried out through temperature cycle test, failure analysis, and finite element modeling. To assess the wafer level package capability and technology limit, the following parameters are considered: WLP structure, array size, ball locations, ball pitch, and temperature cycle profile.Daisy-chain chips are used for this study. Extensive failure analysis was carried out to confirm failure mechanism and quantify the mechanical degradation among different solder joints due to temperature cycle stressing. It is suggested that the primary failure mechanism is solder fatigue. The crack is in bulk solder at package side. The cracks initiate from both sides of the solder joint. The cracks propagate from edge toward the center of the solder ball. The corner balls are most susceptible to solder joint failures. Based on test data, making corner balls electrically not connected improves the WLP reliability by 30%.It is concluded that WLP structure A has superior solder joint reliability compared to B and C. For a given ball array size, smaller pitch gives better solder joint life. The solder joint fatigue life is approximately 1.2 times longer for 2 cycle per hour (cph) conditions than 1 cph temperature cycling condition.

JEDEC board drop test simulation for wafer level packages (WLPs)

“…It should be noted that when equation (3) or (4) is applied, the board response includes a rigid body movement. In other words, the board displacements will be infinite with time increasing.…”

“…Wafer level packaging (WLP) is gaining tremendous interest throughout the semiconductor industry, due to the rapid advances in integrated circuit fabrication and the demands of an emerging market for smaller, thinner, and faster, yet less expensive electronic products [1][2][3]. Waferlevel packaging paves the way for true integration of wafer fab, packaging, test, and burn-in at wafer level, for the ultimate streamlining of the manufacturing process undergone by a device from silicon start to customer shipment.…”

Reliability enhancement of wafer level packages with nano-column-like hollow solder ball structures

“…The displayed results are for the outermost ball in the diagonal direction. Both the maximum and the averaged results are obtained, and the averaged values are calculated according to equation (4). The solder ball height for the regular ball case is considered as the actual height of 234m.…”

“…Both the maximum and the averaged results are obtained. The averaged values are calculated according to equation (4). The solder ball height is considered as the height when polymer cored ball is used for the same diameter of solder ball.…”

“…The ability of solder joints to survive the required thermal cycle testing has limited the WLPs to the products having relatively small die sizes and a small number of I/O [4]. The intrinsic difference in the coefficient of thermal expansion (CTE) between silicon (~2.6ppm/C) and PCB (~17ppm/C) determines that the solder ball thermal cycling fatigue performance is limited by die-size.…”