An accurate analytical delay model for BiCMOS driver circuits

Abstract

In this paper, a new analytical delay model for BiCMOS driver circuits is presented. The model is based on physical device parameters, and can be used to estimate both the pull-up and the pull-down times for a variety of circuit configurations. The intrinsic delay associated with the bipolar transistors is taken into consideration by a charge control model that incorporates the highinjection effects upon the current gain and the base transport factor. Separate sets of delay equations are derived for the pull-up and pull-down transient responses because significant differences are shown to exist between the two cases. The comparison with SPICE circuit simulation results shows that the new model predicts the respective delay times with less than 10% error in most cases. The influence of device dimensions upon the inverter delay time is also investigated. It is demonstrated that an optimal area allocation exists between the CMOS and bipolar parts of the driver circuit if the total available area is limited such as in standard cell configurations.

Design of analog to digital converters for multiple-valued systems

“…Technology parameters of one CMOS process [7] and supply voltages V SS =0V, V DD1 =4V, V DD2 =8V, V DD3 =12V and V DD4 =16V were used in simulations. Voltage CMOS comparator circuits as proposed in the paper [8], with appropriate designed threshold voltages, are used for design of CMOS voltage comparator network of the converter.…”

Multiple-valued regenerative CMOS logic circuits with high-impedance output state

“…when the circuits are symmetrical and for one CMOS technology process [5]. Results for simple circuit in Fig.…”

“…As an illustration of proposed methods, the concrete schemes of such quinternary (logic basis of 5) CMOS logic circuits are given. All proposed principles and circuits have been analyzed and confirmed by PSPICE simulation for one CMOS technology process [5].…”

Influence of BJT Transit Frequency Limit Relationto MOSFET Parameters on the Switching Speedof BiCMOS Digital Circuits

“…BiCMOS is the technology combining the low power of CMOS with the high-speed and drive capability of bipolar for realizing high performance digital circuits [1][2][3]. Over the years BiCMOS integrated circuits have been well characterized for high-speed digital logic applications [4][5][6][7][8][9][10][11][12][13][14][15][16]. The circuit delay time model of the BiCMOS has been extensively studied and as a performance measure of the BiCMOS technology [12].…”

“…The circuit delay time model of the BiCMOS has been extensively studied and as a performance measure of the BiCMOS technology [12]. Many closed-form analytical expressions for the gate delay have been derived through the physical and electrical modeling and are available in the literature [5,9,[10][11][12][13]. Greeneich and McLaughlin [5] have obtained closed-form analytical expressions for the gate delay and have shown its dependence on device and circuit parameters.…”