In this paper, a new analytical delay model for BiCMOS driver circuits is presented. The model is based on physical device parameters, and can be used to estimate both the pull-up and the pull-down times for a variety of circuit configurations. The intrinsic delay associated with the bipolar transistors is taken into consideration by a charge control model that incorporates the highinjection effects upon the current gain and the base transport factor. Separate sets of delay equations are derived for the pull-up and pull-down transient responses because significant differences are shown to exist between the two cases. The comparison with SPICE circuit simulation results shows that the new model predicts the respective delay times with less than 10% error in most cases. The influence of device dimensions upon the inverter delay time is also investigated. It is demonstrated that an optimal area allocation exists between the CMOS and bipolar parts of the driver circuit if the total available area is limited such as in standard cell configurations.
This paper presents a new deep submicron compact physical model for analog circuit simulation. The proposed model, iSIM, \bows not only excellent moderate inversion characteristics for both DC and AC models but also the continuity of currents, conductances, and transcapacitances in all regions of operation. The model evaluation time of iSIM is only half of the SPICE level 2 model
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