Principles and possibilities of synthesis and design of bus interface circuits with high-impedance output state in multiple-valued logic systems are described and proposed in the paper. The general principles for implementation of such circuits are considered first. Then the methods for synthesis and design of logic circuits with high-impedance output state in multiple-valued CMOS logic systems with any logic basis are proposed and described. Two principles of synthesis and implementation of CMOS multiple-valued logic circuits with high-impedance output state are proposed and described: the simple circuits with smaller number of transistors, and the buffer/driver circuits with decreased propagation delay time. As an example, the schemes of such CMOS multiple-valued logic circuits with the logic basis of 5 (quaternary multiple-valued logic circuits) are given and analyzed by computer simulations. Some of computer simulation results confirming descriptions and conclusions are also given in the paper.
The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm includes the most important aspects of design of quaternary logic circuits: logic circuit scheme synthesis and logic circuit optimization. Methods for synthesis of quaternary CMOS combinational logic circuits are proposed and described. Also, method for optimization of CMOS quaternary logic circuits, according to operation conditions and needed characteristics, is proposed and described. Design procedure is realized by personal computer using PSPICE for circuit simulation. Computer PSPICE simulation results confirming described methods and conclusions are given in the paper.
Principles and possibilities of synthesis and design of quaternary multiplevalued regenerative CMOS logic circuits with high-impedance output state are described and proposed in the paper. Two principles of synthesis and implementation of CMOS regenerative quaternary multiple-valued logic circuits with high-impedance output state are proposed and described: the simple circuits with smaller number of transistors, and the buffer/driver circuits with decreased propagation delay time. The schemes of such logic circuits are given and analyzed by computer simulations. Some of computer simulation results confirming descriptions and conclusions are also given in the paper.
Principles and possibilities of synthesis and design of multiple-valued (MV) regenerative CMOS logic circuits with high-impedance output state and any logic basis are proposed and described in the paper. Two principles of synthesis and implementation of CMOS regenerative multiple-valued logic circuits with high-impedance output state are proposed and described: the simple circuits and the buffer/driver circuits. The schemes of such circuits are given and analyzed by computer simulations. Some of computer simulation results confirming descriptions and conclusions are also given in the paper.
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