Multiple-valued cmos logic circuits with high-impedance output state

Abstract

Principles and possibilities of synthesis and design of bus interface circuits with high-impedance output state in multiple-valued logic systems are described and proposed in the paper. The general principles for implementation of such circuits are considered first. Then the methods for synthesis and design of logic circuits with high-impedance output state in multiple-valued CMOS logic systems with any logic basis are proposed and described. Two principles of synthesis and implementation of CMOS multiple-valued logic circuits with high-impedance output state are proposed and described: the simple circuits with smaller number of transistors, and the buffer/driver circuits with decreased propagation delay time. As an example, the schemes of such CMOS multiple-valued logic circuits with the logic basis of 5 (quaternary multiple-valued logic circuits) are given and analyzed by computer simulations. Some of computer simulation results confirming descriptions and conclusions are also given in the paper.

Multiple-valued regenerative CMOS logic circuits with high-impedance output state

“…There are two methods to obtain high-impedance output state in CMOS MV logic circuits: using CMOS transmission gate at MV circuit output, or disconnecting MV circuit output from supply voltages. Realizations of CMOS MV circuits with high-impedance output state are proposed and described in paper [6]. Methods for obtaining of regenerative MV CMOS logic circuits are considered and described in paper [7].…”

“…Given equations (1) and (2) can be used for calculation of threshold voltages. Dynamic characteristics depend on parameters of the circuit in the same way as for standard buffer/driver MV CMOS circuits with high-impedance output state [6].…”