Advanced DUV photolithography in a pilot line environment

Ausschnitt, Christopher P.; Thomas, A.; Wiltshire, Timothy J.

doi:10.1147/rd.411.0021

Cited by 16 publications

(10 citation statements)

References 15 publications

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“…This metric is based on the lithographic process because, historically, the advance from one technology node to the next was determined by lithographic technology. For example, the introduction of deep-UV in the late 1980's enabled the development of 0.5 micron node DRAM [7]. More recently scaling has been constrained by the ramifications of reduced feature size on the performance of the transistor, and the ability of process engineers to overcome these effects.…”

Section: Technology Scalingmentioning

confidence: 99%

Life-Cycle Assessment of Semiconductors

Boyd¹

2012

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This thesis is the first complete and transparent study of the life-cycle environmental impacts of semiconductor chips using process-level data, as well as the first analysis of the changes in these impacts over time. LCA of complementary metal oxide semiconductor (CMOS) logic, flash memory and dynamic random access memory (DRAM) are presented. CMOS logic is the most common form of digital logic used today. This thesis provides a life cycle assessment for CMOS chips over 7 technology generations with the purpose of comparing impacts by life cycle stage, examining their trends over time and evaluating their sensitivity to data uncertainty and changes in production metrics such as yield. A hybrid life cycle assessment (LCA) model is used; Wafer production, electricity generation, water supply and certain materials are represented by process LCA data, while the remaining materials are described using economic input-output (EIO) LCA methods. It is determined that, in the case of CMOS logic, life-cycle impacts in all but one category are dominated by the use phase, and impacts are most sensitive to those variables which define use phase energy demand (chip power demand, usage patterns, power supply efficiency and chip lifetime). Using the same methodology, LCA of flash memory over 5 technology generations is presented. The most recent generation of flash memory is compared with magnetic storage, using a laptop hard-drive as a functional unit, and it is determined that in most impact categories, a flash-based drive will result in fewer impacts. Life-cycle impacts of DRAM, over 6 technology generations, are presented using as the functional unit, the memory requirements a popular operating system in each year of production. The influence of the choice of functional unit on results in semiconductor LCA is examined, and it is argued that functional unit is best defined as a computational power or memory capacity required for a given function, within a set time period. The LCA impact and inventory results for these three types of semiconductor products allow more accurate assessment of the environmental ben-1 efit or costs of information technology relative to traditional products and services.

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Section: Technology Scalingmentioning

confidence: 99%

Life-Cycle Assessment of Semiconductors

Boyd¹

2012

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“…Since image quality is a function of both focus and exposure dose, such resolutions are obtained, in part, by minimizing the resist thickness and limiting the interference from underlying features [6]. The trend toward thinner resists is illustrated in Table 1.…”

Section: Applicationsmentioning

confidence: 99%

Plasma-etching processes for ULSI semiconductor circuits

et al. 1999

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“…Such patterned metal films may offer a low cost alternative to fabricating interconnects in modern semiconductor devices, replacing contemporary evaporative (e.g., aluminum) or electrochemical (e.g., copper) methods of deposition. Sub-micron scale patterning capability of EMD needs to be demonstrated to compete with the current interconnect patterning [10][11][12][13][14] using electrochemical deposition, the so-called dual damascene process [15,16].…”

Section: Introductionmentioning

confidence: 99%

Controlled Deposition of Tin Oxide and Silver Nanoparticles Using Microcontact Printing

2015

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This report describes extensive studies of deposition processes involving tin oxide (SnOx) nanoparticles on smooth glass surfaces. We demonstrate the use of smooth films of these nanoparticles as a platform for spatially-selective electroless deposition of silver by soft lithographic stamping. The edge and height roughness of the depositing metallic films are 100 nm and 20 nm, respectively, controlled by the intrinsic size of the nanoparticles. Mixtures of alcohols as capping agents provide further control over the size and shape of nanoparticles clusters. The distribution of cluster heights obtained by atomic force microscopy (AFM) is modeled through a modified heterogeneous nucleation theory as well as Oswald ripening. The thermodynamic modeling of the wetting properties of nanoparticles aggregates provides insight into their mechanism of formation and how their properties might be further exploited in wide-ranging applications.

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Advanced DUV photolithography in a pilot line environment

Cited by 16 publications

References 15 publications

Life-Cycle Assessment of Semiconductors

Life-Cycle Assessment of Semiconductors

Plasma-etching processes for ULSI semiconductor circuits

Controlled Deposition of Tin Oxide and Silver Nanoparticles Using Microcontact Printing

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