2012
DOI: 10.1007/978-1-4419-9988-7
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Life-Cycle Assessment of Semiconductors

Abstract: This thesis is the first complete and transparent study of the life-cycle environmental impacts of semiconductor chips using process-level data, as well as the first analysis of the changes in these impacts over time. LCA of complementary metal oxide semiconductor (CMOS) logic, flash memory and dynamic random access memory (DRAM) are presented. CMOS logic is the most common form of digital logic used today. This thesis provides a life cycle assessment for CMOS chips over 7 technology generations with the purpo… Show more

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Cited by 35 publications
(27 citation statements)
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“…Moreover, the calibration factors (i.e., carbon emission factor of electricity and OWE) can be adjusted in the proposed parametric carbon footprinting tool to strengthen the application. Although several fast carbon footprinting approaches for the semiconductor industry have been proposed in previous studies (Boyd et al 2006;Dessouky et al 2011;Villard et al 2012), which integrated material and energy consumption with carbon emission at each equipment unit of the manufacturing process, these approaches are suitable for use by a semiconductor company that is capable of completely in-house production, from design to the manufacturing stage. However, this approach may be inapplicable to some semiconductor companies that have separate design and manufacturing stages due to the confidentiality of this internal information of other enterprises.…”
Section: Discussion and Limitationsmentioning
confidence: 99%
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“…Moreover, the calibration factors (i.e., carbon emission factor of electricity and OWE) can be adjusted in the proposed parametric carbon footprinting tool to strengthen the application. Although several fast carbon footprinting approaches for the semiconductor industry have been proposed in previous studies (Boyd et al 2006;Dessouky et al 2011;Villard et al 2012), which integrated material and energy consumption with carbon emission at each equipment unit of the manufacturing process, these approaches are suitable for use by a semiconductor company that is capable of completely in-house production, from design to the manufacturing stage. However, this approach may be inapplicable to some semiconductor companies that have separate design and manufacturing stages due to the confidentiality of this internal information of other enterprises.…”
Section: Discussion and Limitationsmentioning
confidence: 99%
“…The quantity of mask layers represents the level of complexity for wafer (Taiariol et al 2001;Yao et al 2004). Boyd et al (2006) implemented life cycle inventory for a comparison between a six-layer wafer and an eight-layer wafer with the same specifications. The results indicated that the increase in the quantity of layers and the consumption of energy and material will affect the wafer's CFP.…”
Section: Discussion and Limitationsmentioning
confidence: 99%
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