Access resistor modelling for EEPROM’s retention test vehicle

Canet, P.; Postel-Pellerin, J.; Ogier, Jean-Luc

doi:10.1016/j.microrel.2013.07.008

Cited by 3 publications

(2 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It provides for example the possibility to detect overerased bit tails or weaknesses in terms of data retention [2,3]. Furthermore, the problems due to the access resistance of a cell in a memory array can be modeled to optimize the number of contacts to bring the voltage biasing in a specific area without loss [4]. The equivalent transistor of charge storage memory, that corresponds to the memory cell where the floating and control gates are shorted, is also used in CAST structures to study the oxide reliability.…”

Section: Introductionmentioning

confidence: 99%

“…This information is fundamental for the process control of large memory array to detect edge or specific signatures due to the different behaviors. Complex calculation techniques, combined with specific physical analysis [5], are used to estimate the number of extrinsic cells [4]. Finally, only electrical characterization on test products, can show the vulnerability localization [5].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

SuperCAST: a full free addressable memory array

Marca

Guilleau-Tavernier

Laine

et al. 2022

2022 IEEE 34th International Conference on Microelectronic Test Structures (ICMTS)

View full text Add to dashboard Cite

In this paper we present a full free addressable 4kb EEPROM memory array. This test structure based on CAST vehicle has been upgraded with flexible addressing logic to select any numbers of cells on single or multiple word lines. To this aim, column/row shift registers, to enable an easy cell biasing, have been implemented in an embedded non-volatile memory environment. High voltage circuits, driven by low voltage shift registers, are used to bias selected cells for electrical characterizations and reliability tests purposes. This kind of structure has been developed to improve the efficiency of electrical characterization laboratory, resulting in an enhanced acquisition with respect to standard CAST test techniques, opening the path to fine statistical analysis.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

SuperCAST: a full free addressable memory array

Marca

Guilleau-Tavernier

Laine

et al. 2022

2022 IEEE 34th International Conference on Microelectronic Test Structures (ICMTS)

View full text Add to dashboard Cite

show abstract

Impact of resistive paths on NVM array reliability: Application to Flash & ReRAM memories

Canet

Postel-Pellerin

Aziza

2016

Microelectronics Reliability

View full text Add to dashboard Cite

Simulation of the programming efficiency and the energy consumption of Flash memories during endurance degradation

Postel-Pellerin

Chiquet

Marca

2016

2016 International Semiconductor Conference (CAS)

View full text Add to dashboard Cite

International audienceIn this paper the impact of the endurance degradation on the programming window and the energy consumption of Flash floating gate memories is investigated. We use TCAD simulations to confirm, predict and explain the behavior we have observed in previous experimental studies. These simulations have been developed for 90nm technology node Flash floating gate memories, but they are fully compatible with highly scaled devices. The use of interface traps in the simulation enables to reproduce the increase in the drain current consumption and the decrease in the programming efficiency after endurance degradation. Moreover, we highlight the fact that after degradation the hot electrons energy and velocity are lower, decreasing the electrons injection in the floating gate

show abstract

Access resistor modelling for EEPROM’s retention test vehicle

Cited by 3 publications

References 4 publications

SuperCAST: a full free addressable memory array

SuperCAST: a full free addressable memory array

Impact of resistive paths on NVM array reliability: Application to Flash & ReRAM memories

Simulation of the programming efficiency and the energy consumption of Flash memories during endurance degradation

Contact Info

Product

Resources

About