AC Transconductance Dispersion (ACGD): A Method to Profile Oxide Traps in MOSFETs Without Body Contact

Sun, Xiao Wei; Cui, Sharon; Alian, A.; Brammertz, Guy; Merckling, Clément; Lin, Dennis; P., T.

doi:10.1109/led.2011.2181318

Cited by 27 publications

(19 citation statements)

References 17 publications

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“…The spatial distribution of border traps was evaluated from the border trap capacitance, ΔC bt , and the time constant of trapping, τ(x) [7,12]. The latter increases exponentially with tunneling depth, x, see (1), and provides the upper frequency limit for which a trap at depth x is able to respond [12].…”

Section: Transistor Border Trap Modelmentioning

confidence: 99%

“…Here, it is assumed that for an incremental change in frequency between ω and ω-δω, all traps at a thickness x around a point x m charge and discharge during one cycle [7].…”

Section: An Analytical Expression Is Deduced For Simple Calculations mentioning

confidence: 99%

“…Furthermore, it is often only the interface traps that are considered when using these methods. Recently, Sun et al reported on a method with frequency dependent transconductance, g m (ω), measurements in the 10 1 -10 4 Hz frequency range for characterization of very deep border traps [7]. By extending the frequency range of the transconductance measurements to much higher frequencies, e.g.…”

Section: Introductionmentioning

confidence: 99%

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A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs

Johansson

Berg

Persson

et al. 2013

IEEE Trans. Electron Devices

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Section: Transistor Border Trap Modelmentioning

confidence: 99%

“…Here, it is assumed that for an incremental change in frequency between ω and ω-δω, all traps at a thickness x around a point x m charge and discharge during one cycle [7].…”

Section: An Analytical Expression Is Deduced For Simple Calculations mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs

Johansson

Berg

Persson

et al. 2013

IEEE Trans. Electron Devices

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“…The role of II-VI layers as gate insulators to improve the threshold voltage variation is considered in light of interface states. 18 Future work in this project is to fabricate sub-22-nm devices to study the threshold voltage stability at nanometer gate widths. These devices promise to show very high switching speed due to the single-crystalline nature.…”

Section: Discussionmentioning

confidence: 99%

Fabrication and Simulation of InGaAs Field-Effect Transistors with II–VI Tunneling Insulators

Suarez¹,

Chan

Gogna

et al. 2015

Journal of Elec Materi

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This study shows the use of a high-j ZnS/ZnMgS/ZnS heteroepitaxial tunneling layer in an InGaAs field-effect transistor. Experimental fabrication and simulation of this semiconductor structure show promise of reducing threshold voltage variation by replacing silicon and hafnium oxides as a gate insulator. The II-VI tunneling insulator is grown on an InGaAs substrate using ultraviolet-irradiated metalorganic vapor-phase epitaxy. GeO x -Ge cladded quantum dots are self-assembled to form the gate material. The gate consists of two self-assembled individually cladded quantum dot layers which allow multilogic behavior. Simulations calculated by solving the Schrödinger and Poisson equations self-consistently confirm experimental I D -V D characteristics and show the electron distribution in an inversion channel/quantum well under different gate voltage bias values.

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“…1(b)). The g m (f) dependence in high-κ InGaAs MOSFETs is generally modeled by cold carrier trapping into the oxide [8]- [10]. A similar model is used to explain the small stable I d V g hysteresis found also in early high-κ/silicon devices [11].…”

Section: Devices and Measurementmentioning

confidence: 99%

RF and DC Analysis of Stressed InGaAs MOSFETs

Roll

Lind

Egard

et al. 2014

IEEE Electron Device Lett.

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Abstract-A complete reliability study of the DC and RF characteristics for InGaAs nMOSFETs with Al2O3/HfO2 dielectric is presented. The main stress variation at high frequencies is related to a threshold voltage shift, whereas no decrease is found in the maximum of the cut-off frequency and RF-transconductance. Constant gate stress leads to a charge build up within the gate oxide causing a threshold voltage shift. Furthermore, electron trapping at the drain side degrades the performance after hot carrier stress. The maximum DC-transconductance is reduced following constant gate bias stress, by an increase in charge trapping at border defects. These border defects at the channel/high-κ interface are filled by cold carrier trapping when the transistor is turned on, whereas they do not respond at high frequencies.

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AC Transconductance Dispersion (ACGD): A Method to Profile Oxide Traps in MOSFETs Without Body Contact

Cited by 27 publications

References 17 publications

A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs

A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs

Fabrication and Simulation of InGaAs Field-Effect Transistors with II–VI Tunneling Insulators

RF and DC Analysis of Stressed InGaAs MOSFETs

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