A Wideband RF Mixing-DAC Achieving IMD &lt; -82 dBc Up to 1.9 GHz

Bechthum, Elbert; Radulov, Georgi; Briaire, J.; Geelen, Govert; Roermund, Arthur van

doi:10.1109/jssc.2016.2543703

Cited by 40 publications

(20 citation statements)

References 13 publications

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“…3 a Mixing logic operation by XNOR-gating the input bit and the clock, b bipolar pulse amplitude modulation (PAM) to generate the RF DAC frequency response, and c simplified equivalent circuit at each clock phase and hence the total output impedance is always constant and it does not contribute to the linearity degradation. This can be also observed from (2) where the output voltage is a linear function of the input code and there is no codedependent load variation which was a limiting factor in current steering DACs.…”

Section: Transfer Functionmentioning

confidence: 74%

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A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

Sadeghifar

Bengtsson

Wikner

2019

Analog Integr Circ Sig Process

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As the number of antenna elements increases in massive multiple-input multiple-output-based radios such as fifth generation mobile technology (5G), designing true multi-band base-station transmitter, with efficient physical size, power consumption and cost in emerging cellular frequency bands up to 10 GHz, is becoming a challenge. This demands a hard integration of radio components, particularly the radio's digital application-specific integrated circuits (ASIC) with high performance multi-band data converters. In this work, a novel radio frequency digital-to-analog converter (RF DAC) solution is presented, that is also capable of monolithic integration into today's digital ASIC due to its digital-in-nature architecture. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone. This 12-bit RF DAC is designed in a 22 nm FDSOI CMOS process, and shows excellent linearity performance for output frequencies up to 10 GHz, with no calibration and no trimming techniques. The achieved linearity performance is able to fulfill the high requirements of 5G base-station transmitters. Extensive Monte-Carlo analysis is performed to demonstrate the performance reliability over mismatch and process variation in the chosen technology.

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Section: Transfer Functionmentioning

confidence: 74%

“…RF DAC or RF-sampling DAC, in this context, refers to DACs for which the sample rate is high and the DAC output is in RF domain [2,3,15,18]. Depending on the architecture and implementation choices, the RF DAC can utilize first, second or even higher Nyquist zones to synthesize the signal at the desired RF frequency.…”

Section: Rf-sampling Dacsmentioning

confidence: 99%

A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

Sadeghifar

Bengtsson

Wikner

2019

Analog Integr Circ Sig Process

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“…5(b). Implementation and measurements of this architecture are discussed in [29]. Those measurements show that the proposed architecture can indeed achieve a high spectral purity.…”

Section: Classification Overviewmentioning

confidence: 99%

Classification for synthesis of high spectral purity current-steering mixing-DAC architectures

Bechthum

Radulov

Briaire³

et al. 2015

Analog Integr Circ Sig Process

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This paper proposes a classification of Mixing-DAC architectures, focusing on spectral purity. Based on literature research, analysis and simulations, the proposed classification shows the impact of architectural choices on the output spectral purity. To concretize the classification and validate the analysis, a number of specific Mixing-DAC architectures are synthesized, discussed and simulated. Given the proposed classification, a set of optimal architectural choices lead to a strong architecture candidate for achieving high spectral purity at high signal frequencies, i.e. SFDR [ 80 dBc at f OUT = 4 GHz for current and future multicarrier GSM applications. The main characteristics of this architecture are: Cartesian signaling, local Gilbert-cell mixing and a fully differential implementation.

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“…One key performance metric for its high-speed and wideband applications is the dynamic linearity, usually evaluated as the spurious-free dynamic range (SFDR). Meanwhile, the signal bandwidth and the location of the band of interest vary from one application to another, [27][28][29] which indicates power-performance codesign opportunities for DAC operation optimization based on the specific application requirement on the signal being converted. [1][2][3][4][5][6][7][8][9][10][11] Techniques used to improve the SFDR in high-speed applications rely on more stringent clocking 1,2,12-20 (eg, half-cycle sampling) or increased area [3][4][5][6][7][8]19,[21][22][23][24] (eg, 2 interleaved sub-DACs).…”

Section: Introductionmentioning

confidence: 99%

“…Although the dynamic linearity is increased with these techniques, extra power consumption shortens battery life for edge devices, eg, fielded software-defined portable radio stations 25 and 5G handset transmitters, 26 where low-power design of high-performance wideband DACs is highly preferred. Meanwhile, the signal bandwidth and the location of the band of interest vary from one application to another, [27][28][29] which indicates power-performance codesign opportunities for DAC operation optimization based on the specific application requirement on the signal being converted. Therefore, understanding the existing bottlenecks for potential design space extension may enable a new paradigm of power savings.…”

mentioning

confidence: 99%

Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

Lai

Yang

2018

Circuit Theory & Apps

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This paper presents redundancy-bandwidth scalable techniques to deal with the intersymbol interference distortions for current-steering digital-to-analog converters in high-speed applications. A switching strategy that explores the use of redundant current sources is proposed to realize a signal-independent element transition rate, ie, the number of switching activities during the transition of successive sampling clock cycles. With a certain number of redundant current sources, this strategy significantly reduces the intersymbol interference distortions without oversampling operation or causing signal attenuation, which makes it appealing for high-speed applications. As analyzed in this paper, the number of required redundant current sources is scalable for different bandwidth requirement in specific applications, leading to 3 redundancy-bandwidth scalable trade-offs between the cost from redundant current sources and the high-dynamic-range bandwidth. In implementation, we propose a customdesigned decoder, named as the overlap-controlled data-weighted averaging (OC-DWA). Compared with the existing similar-purpose designs, the proposed OC-DWA decoder realizes the current sources selection with a simple barrel rotator, which is of much lower hardware complexity and energy consumption.Simulations of a digital-to-analog converter with this decoder exhibit an enhanced dynamic range over the entire Nyquist band, which verifies the redundancy-bandwidth scalability of the proposed techniques.

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A Wideband RF Mixing-DAC Achieving IMD < -82 dBc Up to 1.9 GHz

Cited by 40 publications

References 13 publications

A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

Classification for synthesis of high spectral purity current-steering mixing-DAC architectures

Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

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