A wide input voltage range level shifter circuit for extremely low-voltage digital LSIs

This paper proposes a high-speed and ultra-low power level shifter (LS) capable of realizing wide-range voltage level conversion. Two key features are contained in the presented LS to support its superior performances. First, a novel boost control circuit is proposed to boost input voltage and strengthen pull-down driven capability, which results in significant improvement of operation speed and conversion range. Second, multi-threshold COMS (MTCMOS) and sub-threshold device sizing techniques are employed to reduce the static current, thereby obtaining ultra-low leakage power consumption. Post-layout simulation results demonstrate that the proposed LS implemented with SMIC 55-nm technology can convert 140mV lowvoltage to 1.2V. Meanwhile, when evaluated with the low supply voltage of 0.3V at 1MHz frequency, the transition energy of the presented LS is 87.35 fJ. Moreover, the static power consumption and propagation delay are only 64.2 pW and 18.07ns, respectively.

Section: Introductionmentioning

confidence: 99%

A fast and low-power level shifter for multi-supply voltage designs

Yin

Jia

You

et al. 2020

“…To realize robust conversions between large supply voltage differences, several level shifters have been proposed [15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32]. In order to balance the strength of the pull-up and pull-down networks in cross-coupled based level shifter, in [18,26], diode current limiters are inserted in the pull-up networks to reduce the pull-up strength.…”

Section: Introductionmentioning

confidence: 99%

An ultra-low leakage energy efficient level shifter with wide conversion range

You

Jia

Tang

et al. 2019

An ultra-low leakage energy efficient level shifter that can convert extremely low input voltage into the supply voltage level is presented in this paper. In order to reduce the leakage power dissipation, the super-cutoff mechanism and MTCMOS technique are utilized in the proposed structure. At the same time, a positive feedback circuit is inserted to avoid the loss of performance. Post-layout simulation results in a 55-nm MTCMOS process demonstrate that for the voltage level conversion from 0.3 V to 1.2 V, the proposed level shifter exhibits a propagation delay of 70.77 ns and an energy per transition of 89.55 fJ for input frequency of 1 MHz. Meanwhile, the static power of the proposed level shifter is as low as 27.82 pW. The proposed level shifter only occupies 7.79 um 2 , which demonstrates prominent area efficiency.

“…WLS has significantly better speed performance and energy efficiency; however, the output node of the current-mirror floats for a high level of V IN which causes a significant detrimental effect on the output buffer. An LS with logic-error correction (LSLEC), proposed in [8], uses the current generators (CGs) that supply current when the logic level of the output is not corresponding to the logic level of the input. Contention problem of LSLEC is discussed in [9] where they propose a new LS using CGs and solve the problem by feeding back the output signal.…”

Section: Introductionmentioning

confidence: 99%

Energy efficient low static-power voltage level shifter

Maroof

Sohail

Shin

2015

Level shifter circuits are necessary parts of modern SoCs, as they interface different voltage domain signals. This paper presents an energyefficient level up shifter capable of converting sub-threshold input signal to higher levels. The proposed design uses the feedback mechanism of a regulated gate cascode to achieve energy efficient operation. Once the desired output level is achieved, large static current does not flow, and static power is further minimized using a transistor stack. Implementing in a 90-nm process, post-layout simulation results show that the proposed level shifter has a propagation delay of 21.2 ns, a total energy-per-transition of only 77.5 fJ, and a static power dissipation of 7.2 nW.