Abstract:This paper proposes a high-speed and ultra-low power level shifter (LS) capable of realizing wide-range voltage level conversion. Two key features are contained in the presented LS to support its superior performances. First, a novel boost control circuit is proposed to boost input voltage and strengthen pull-down driven capability, which results in significant improvement of operation speed and conversion range. Second, multi-threshold COMS (MTCMOS) and sub-threshold device sizing techniques are employed to r… Show more
“…In reference [15], two conventional LS architectures are discussed: the current mirroring (CM) and the differential cascading voltage switching (DCVS) models. However, this approach is accompanied by significant power consumption when dealing with highvoltage input signals, hence making it less suitable for low-power devices.…”
Section: Introduction and Literature Surveymentioning
The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm2. These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field.
“…In reference [15], two conventional LS architectures are discussed: the current mirroring (CM) and the differential cascading voltage switching (DCVS) models. However, this approach is accompanied by significant power consumption when dealing with highvoltage input signals, hence making it less suitable for low-power devices.…”
Section: Introduction and Literature Surveymentioning
The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm2. These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field.
“…This model has latency and area of 27.08 ns and 47.78 μm 2 respectively. In [7], Current-mirror (CM) and differential cascade voltage switch (DCVS) structures are the two most common forms of traditional LSs. However, when dealing with high supply voltage (VDDH), the CM structure results in considerable static power waste owing to leakage current via the transistors.…”
The Level Shifter is made with two inverters and a Wilson current mirror to use less energy. In order to reduce the amount of leaking power, this study suggests using a combination of super-cut-off draw-down and stacked pull-up networks. The design also incorporates MTCMOS technology, which, consists of sleeper transistors that are able to boosts performance without increasing either power usage or size. The designed device can be used to shift voltage in between 0.4 V and 1.2 V. To suit nano-scale uses, the circuit's operating range and performance factors (such as power, latency, and area) were fine-tuned. According to the results, "level-up" transitions typically consume 148.6nW of active power and have an average delay of 1.19 ns at 1 MHz transmission rates. The post-layout model indicated that the recommended plan would need 9.47 µm2 of floor space. The results are analyzed in Cadence Virtuoso using 45nm techniques.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.