A VLSI systolic array architecture for Lempel-Ziv-based data compression

A high-throughput lossless data compression IP core built around a CAM-based dictionary whose number of available entries and data word width adjust to the characteristics of the incoming data stream is presented. These two features enhance model adaptation to the input data, improving compression efficiency, and enable greater throughputs as a multiplicity of bytes can be processed per cycle. A parsing mechanism adjusts the width of dictionary words to natural words while the length of the dictionary grows from an initial empty state to a maximum value defined as a run-time configuration parameter. The compressor/decompressor architecture was prototyped on an FPGA-based PCI board. An ASIC hard-macro was subsequently implemented and achieved a throughput of more than 1 gigabyte per second when clocking at 277 MHz on a high-performance, 0.13 mm, eight-layer copper CMOS process.

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A low-power CAM design for LZ data compression

Lin

2000

IEEE Trans. Comput.

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ÐLow-power and high-performance data compressors play an increasingly important role in the portable mobile computing and wireless communication markets. Among lossless data compression algorithms for hardware implementation, LZ77 is one of the most widely used. For real-time communication, some hardware LZ compressors/decompressors have been proposed in the past. Content addressable memory (CAM) is widely considered as the most efficient architecture for pattern matching required by the LZ77 compression process. In this paper, we propose a low-power CAM-based LZ77 data compressor. By shutting down the power for unnecessary comparisons between the CAM words and the input symbol, the proposed CAM architecture consumes much lower power than the conventional ones without noticeable performance penalty. Moreover, using the proposed conditional comparison mechanism and the novel CAM cell with the NAND-type matching logic, on average we have close to two orders of improvement on power consumption, i.e., a reduction of more than 98 percent for 8-bit words. Speed is sacrificed if we use the NAND-type matching logic, but the NAND-type logic and the NOR-type logic can be combined to provide the best solution that balances power and delay. Our approach also can be applied to general-purpose CAMs which use the valid bits, so far as the proposed design techniques are adopted.

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A VLSI systolic array architecture for Lempel-Ziv-based data compression

Cited by 9 publications

References 6 publications

Hardware Implementation of Data Compression

Hardware Implementation of Data Compression

Gigabyte per second streaming lossless data compression hardware based on a configurable variable-geometry CAM dictionary

A low-power CAM design for LZ data compression

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