Gigabyte per second streaming lossless data compression hardware based on a configurable variable-geometry CAM dictionary

Abstract

A high-throughput lossless data compression IP core built around a CAM-based dictionary whose number of available entries and data word width adjust to the characteristics of the incoming data stream is presented. These two features enhance model adaptation to the input data, improving compression efficiency, and enable greater throughputs as a multiplicity of bytes can be processed per cycle. A parsing mechanism adjusts the width of dictionary words to natural words while the length of the dictionary grows from an initial empty state to a maximum value defined as a run-time configuration parameter. The compressor/decompressor architecture was prototyped on an FPGA-based PCI board. An ASIC hard-macro was subsequently implemented and achieved a throughput of more than 1 gigabyte per second when clocking at 277 MHz on a high-performance, 0.13 mm, eight-layer copper CMOS process.

Test Compression for Dynamically Reconfigurable Processors

“…To the best of our knowledge, we first have achieved an over-GB/s peak decompression bandwidth as a rule-based compression approach. For reference, the fastest circuit as a dictionarybased compression approach has already achieved an over-GB/s peak decompression bandwidth (1.092 GB/s) at the fabrication of a 130-nm technology node [21]. We have confirmed that our DPC decompression circuit, which is designed for a 40-nm DRP product, successfully loads actual test configurations to the product.…”

Design-for-Debug Architecture for Distributed Embedded Logic Analysis

“…It is obvious that the amount of debug data one can acquire is limited by the capacity of trace buffers. As a result, trace compression techniques (e.g., [21]- [26]) were proposed to compress debug data on-chip before being stored into trace buffers (Label 2). More recently, data restoration techniques were proposed to improve functional observability [27], [28].…”

Test compression for dynamically reconfigurable processors

“…The compared circuits are an advanced X-Match circuit [Nunez-Yanez and Chouliaras 2006], which has achieved an over-GB/s peak decompression bandwidth (1.092 GB/s) as a dictionary-based compression approach, and a GZIP circuit [AHA 2009], which has the second highest decompression bandwidth (see Figure 8). For reference, we add a 130-nm DPC decompression circuit to the table since the X-Match circuit is fabricated at a 130-nm technology node.…”