Design-for-Debug Architecture for Distributed Embedded Logic Analysis

Abstract

In multi-core designs, distributed embedded logic analyzers with multiple trigger units and trace buffers with real-time offload capability through high-speed trace ports can be placed on-chip. This brings new challenges on how to connect the debug units together in such way that the limited storage space in the trace buffers can be used efficiently. This problem is further aggravated when shadow registers are used to capture data for some signals in the design. In this paper, we propose a new architecture that can dynamically allocate the trace buffers at runtime based on the needs for debug data acquisition coming from multiple data sources and user-programmable priorities. Experimental results show that using the proposed architecture, real-time observability can be improved using only a small amount of on-chip logic hardware, while avoiding excessive storage on-chip.Index Terms-Design-for-debug, distributed embedded logic analysis, post-silicon validation, real-time observability.

On-Chip Debug Architecture for Multicore Processor

“…The entire on-chip debug infrastructure is controlled and programmed through an IEEE 1149.1 JTAG. Although it was originally developed for I/O testing, the IEEE 1149.1 JTAG has become a default interface method for other on-chip test/debug features, including embedded debug blocks commonly available for processor cores [12], [34]. To provide specific debug/test functions depending on the target application, the JTAG can be modified and extended by supporting additional user-defined JTAG instructions or adding special purpose registers and functional blocks [5], [7], [35], [36].…”

“…Although, the real-time trace scheme is a more efficient debugging solution than the run-stop scheme, with respect to supported debugging capability, it may not be the appropriate debug solution in some cases due to complexity and hardware overheads. It requires on-chip or off-chip memory to store the traced debug data and a set of trace ports to transfer debug data out of the chip at high speeds, and it also needs an efficient compression/decompression hardware to reduce the amount of debug data [6], [8], [12].Different from the above conventional processor-centric debug solutions focusing on the processor's computational operations and its interaction with main memory, in recent years, new research has introduced communication-centric debug solutions for network-on-chip (NoC)-based multicore processors to make the interactions between the intellectual property (IP) blocks via the communication architecture observable and controllable [13]- [15].Among the diverse debug approaches, the processor-centric debug solution employing the run-stop scheme gives the developer more power to observe the functional behavior of the processor core at the exact possible erroneous point, in a controlled manner. This debug method allows each embedded processor core of the multicore processor to be controlled and accessed independently.…”

“…Although, the real-time trace scheme is a more efficient debugging solution than the run-stop scheme, with respect to supported debugging capability, it may not be the appropriate debug solution in some cases due to complexity and hardware overheads. It requires on-chip or off-chip memory to store the traced debug data and a set of trace ports to transfer debug data out of the chip at high speeds, and it also needs an efficient compression/decompression hardware to reduce the amount of debug data [6], [8], [12].…”

A debug scheme to improve the error identification in post-silicon validation

“…However, the number of consecutive debug cycles is limited by the size of the trace buffer [7]. Therefore, some debug techniques have applied a multiple-input signature register (MISR) to compact the debug cycles and to observe the generated signatures [8, 9, 10, 11]. The signatures generated by MISR are unloaded to an external debugger and compared with the golden signatures to determine whether the signatures are erroneous.…”

An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time

“…Real-time signal tracing methods were researched to support each debug phase [8], [10], [11], [12], [14]. These approaches include an embedded logic analyzer consisting of trigger units, a sample unit, and an offload unit.…”