An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time

Abstract

Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chip error detection method to overcome this challenge. The on-chip process detects the error-suspect window using the pre-calculated golden data stored in the trace buffer. This allows the selective compaction and capture of the debug data in the trace buffer during the error-containing interval. As a result, reducing the number of debug sessions significantly reduces the total debug time. The experimental results on various debug cases show significant reductions in total debug time compared to previous work.

A debug scheme to improve the error identification in post-silicon validation

“…The debug scheme in [11] was proposed to reduce the debug time by comparing with [9]. In the debug work in [11], the main debug framework is based on the repeatable debug sessions introduced in [9].…”

“…In the debug work in [11], the main debug framework is based on the repeatable debug sessions introduced in [9]. In the debug approach in [11], the MISR compaction ratio is reduced as the debug session is progressed in a similar manner as [9]. In this case, the golden signatures are pre-stored in the trace buffer before the debug session.…”

“…Therefore, the consecutive debug sessions are performed simultaneously, then the overall debug time can be reduced by comparing with [9]. Nevertheless, the debug approaches in [9, 11] are unsuitable for nondeterministic debug phase because a number of repeatable debug sessions are required to observe the error-suspect interval. For this reason, these debug approaches focus on only the deterministic debug phase and the cycle-accurate error occurrence.…”

“…Fig 1 summarizes the previous debug techniques in [9, 11, 12, 13] in accordance with the usage of the signatures and the identification of the error-suspect debug cycles.…”

“…However, the number of consecutive debug cycles is limited by the size of the trace buffer [7]. Therefore, some debug techniques have applied a multiple-input signature register (MISR) to compact the debug cycles and to observe the generated signatures [8, 9, 10, 11]. The signatures generated by MISR are unloaded to an external debugger and compared with the golden signatures to determine whether the signatures are erroneous.…”