On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug

Abstract

Post-silicon debug has become important with the increased complexity of circuit designs. However, the increase in debug resource costs owing to improved observability has posed a major challenge. To overcome this challenge, this study proposes on-chip error detection that reuses built-in self-repair (BISR). The proposed method utilizes the components of BISR as storages of golden signatures and comparators for error detection. Also, it detects error-suspect cycles more precisely by using parent and child multiple-input signature registers (MISRs). In addition, it provides selective capture and store methods that selectively capture error-suspect debug data in buffers and store them in the DRAM, respectively. The experimental results of various debug cases demonstrate that the proposed method significantly reduces the buffer size, DRAM usage, and debug time compared to previous methods.INDEX TERMS Post-silicon debug, error detection, dynamic random-access memory (DRAM) usage, debug time, area overhead, built-in self-repair (BISR), multiple-input signature register (MISR), threedimensional integrated circuit (3D-IC)

ADKNN fostered BIST with Namib Beetle optimization algorithm espoused BISR for SoC-based devices

“…The 1 st phase verifies the failure detected by the memory built-in self test (MBIST) controller via repaired memory testing. The 2 nd phase obtains the signature of repair to repair the memory [2], [3]. Furthermore, the built-in redundancy analysis approach evaluates the repair signatures based on memory failure information and implements the memory redundancy technique [4].…”