A debug scheme to improve the error identification in post-silicon validation

Abstract

While developing semiconductors, post-silicon validation is an important step to identify the errors that are not detected during the pre-silicon verification and manufacturing testing phases. When the design complexity increases, the required debug time also increases because additional debug data are required to identify the errors. In this study, we present a debug scheme that improves the error identification capability. The proposed debug approach concurrently generates three types of signatures using hierarchical multiple-input signature registers (MISRs). The error-suspect debug cycles are determined by analyzing the debug cycles that are commonly contained in the erroneous signatures of the three MISRs. To reduce the amount of debug data, we compare the high-level MISR signatures in real time with the golden signatures; further, we handle the remaining two MISRs based on the tag bits that are obtained from the results of the high-level MISR. The experimental results prove that the proposed debug structure can significantly improve the error identification capability using less debug data than that used in previous debug structure.

On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug

“…To detect error cycles more precisely, on-chip error detection is performed using hierarchical MISRs during the debug experiment. In the trace-buffer-based silicon debug method, error detection methods that use MISRs have been introduced [15]- [18]. However, the main difference between the existing trace-buffer-based methods and the proposed method is whether the error data detection and capture process are performed in real-time.…”

“…The trace buffer-based method is effective for observing real-time debug data for the post-silicon debug; however, its main challenge is the limited observability because the trace buffer size is limited, and it results in DfD hardware overhead. To increase the trace buffer observation, state restoration methods [12], [13] and debug data compression techniques [14]- [18] have been introduced. Nonetheless, trace buffer-based methods still require an exceptionally long debug time.…”

“…The proposed silicon debug method using such conventional BISRs is aimed to improving the quality of error detection by using shorter debug interval detection and reducing the buffer size, DRAM usage, and total debug time. In addition, it is important to note that a cycleaccurate deterministic debug environment is not an impractical assumption [15]- [18], [23]- [28]. Typically, the silicon debug comprises two phases: nondeterministic and deterministic.…”

“…In the deterministic phase, failures can be regulated by using the abovementioned methods. The main objective of the deterministic phase is to detect the root cause in terms of space (erroneous logic) and time (exact clock cycle when the debug occurs) information as rapidly as possible by using golden data calculated through simulations using the behavioral model of the circuit [15]- [18]. Therefore, the proposed method focuses on a cycle-accurate deterministic debug environment.…”

Region-Aware Trace Signal Selection Using Machine Learning Technique for Silicon Validation and Debug

“…Note that, modeling 1 is not been probable for larger extent. So the design bugs are mapped into netlist level [Choi, Jung, Oh et al (2018)] such as unintended wire exchange, gate level random gate replacement, etc. If the two wires are exchanged due to the design error and it slips to fabricated silicon, then that error will propagate to the logical cone of a connected path.…”