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ÐLow-power and high-performance data compressors play an increasingly important role in the portable mobile computing and wireless communication markets. Among lossless data compression algorithms for hardware implementation, LZ77 is one of the most widely used. For real-time communication, some hardware LZ compressors/decompressors have been proposed in the past. Content addressable memory (CAM) is widely considered as the most efficient architecture for pattern matching required by the LZ77 compression process. In this paper, we propose a low-power CAM-based LZ77 data compressor. By shutting down the power for unnecessary comparisons between the CAM words and the input symbol, the proposed CAM architecture consumes much lower power than the conventional ones without noticeable performance penalty. Moreover, using the proposed conditional comparison mechanism and the novel CAM cell with the NAND-type matching logic, on average we have close to two orders of improvement on power consumption, i.e., a reduction of more than 98 percent for 8-bit words. Speed is sacrificed if we use the NAND-type matching logic, but the NAND-type logic and the NOR-type logic can be combined to provide the best solution that balances power and delay. Our approach also can be applied to general-purpose CAMs which use the valid bits, so far as the proposed design techniques are adopted.

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CMOS Exclusive-OR (EXOR) gate implementation using conventional logic structures results in high hardware cost and long propagation delay, making it unattractive to logic designers. A number of more efficient two-input CMOS EXOR-gate structures with only six transistors have been proposed in the past. In many applications, such as parity generator, checker, and Exclusive-OR Sum-of-Product (ESOP) circuits, multiple-input EXOR circuits are required. Two kinds of multiple-input EXOR circuit structures are presented, which are smaller, faster, and more power-saving than those formed by simply connecting two-input EXOR gates in a conventional way. The proposed structures are shown to be suitable for ESOP circuits in which four transistors can be saved for each product term. The reduction in area and power makes them attractive for low-power required applications such as mobile computing and wireless communications.