In this paper we present a gmphical CAD tool, Army Estimaior(ARREST), for VLSI array architectures. In real VLSI armp, piece-wise regular compdaiions are spread across space and time and occur at a fine-grain, which can make visualization quite dificult. Consequently, a gmphical interface environment is desimble io enhance the design, verification, and analysis of VLSI a m y s by providing feedback at all levels of the design process. ARREST reads a high Zevel description of structured VLSI algorithms in terms of Afine Recurrence Equations(AREs) and permits a h a d mnge of tmnsformations on the algorithm. The system does not target a fully automated design process, instead it provides a designer with a means to systematically ezplore various army architectures and evaluate design tmde-08s between VLSI cost and performance. To allow a human designer better insight into the design process, ARREST uses the Xi/MOTIF window system for graphics and interfaces to the Cadence VERILOG simulator.

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