ARREST: an interactive graphic analysis tool for VLSI arrays

Abstract

In this paper we present a gmphical CAD tool, Army Estimaior(ARREST), for VLSI array architectures. In real VLSI armp, piece-wise regular compdaiions are spread across space and time and occur at a fine-grain, which can make visualization quite dificult. Consequently, a gmphical interface environment is desimble io enhance the design, verification, and analysis of VLSI a m y s by providing feedback at all levels of the design process. ARREST reads a high Zevel description of structured VLSI algorithms in terms of Afine Recurrence Equations(AREs) and permits a h a d mnge of tmnsformations on the algorithm. The system does not target a fully automated design process, instead it provides a designer with a means to systematically ezplore various army architectures and evaluate design tmde-08s between VLSI cost and performance. To allow a human designer better insight into the design process, ARREST uses the Xi/MOTIF window system for graphics and interfaces to the Cadence VERILOG simulator.

VLSI array synthesis for polynomial GCD computation and application to finite field division

“…Special purpose array processors are frequently used due to the inherent regularity and locality of such computations. Array architectures are built based on various VLSI costs (area, period, and latency), and the following characteristic are required to exploit the computational regularity and locality as a parallel system: 1) simple processing element; 2) regular connection; 3) concurrency; 4) balanced computation with YO operation. This design philosophy of array processing has been successfully used to map many digital signal processing algorithms to efficient VLSI implementations.…”

“…Many regular algorithms can be expressed in afJine recurrence equation ( structures and to extract structural information in a behavioral level. A structured high-level description language (SHDL), developed at UMASS as an input description format for an array estimation tool (ARREST) [4], is an example. Many algorithmic transformations can be performed at this level for further exploitation: such as localization [ 111, U 0 transformation, control insertion, dynamic dependency removal [8], and others.…”

A NEW PLATFORM FOR THE IMPLEMENTATION OF REGULAR ITERATIVE ALGORITHMS INTO FPGAs

“…STAR 24 is a synthesis system producing data paths in order to create a circuit, given an SFG. ARREST 25 is a graphical analysis environment that manually converts URE and a¯ne recurrence equation (ARE) formatted algorithms in DGs and SFGs. ALIAS 26 creates graphical mappings of synthesis designs, given a single assignment algorithm that describes matrix computations.…”

Εμπέδωση πίνακα επεξεργαστών μέσα σε προγραμματιζόμενο κύκλωμα FPGA, βάσει αφηρημένων μοντέλων για σύνθεση (abstraction models for synthesis) και κάτω από περιορισμούς εβδαδού - χρονισμών

“…• Formals ο πως τα ADVIS [118], SDEF [119], SYSTARS [120], HIFI [121], SYS 3 [122], SILAGE [123], ARREST [124], ALIAS [125], ALPHA [126], APPROVAL [127] και το VASS [128]. Στην περι πτωση αυτη οι αλγο ριθμοι μετασχηματι ζονται ε τσι ω στε να προκυ ψουν ομοιο μορφοι πι νακες επεξεργαστω ν. Αυτε ς οι ο ψεις ελε γχονται προκειμε νου οι εξαρτη σεις δεδομε νων να μπορε σουν να απεικονιστου ν πα νω στους διαδρο μους επικοινωνι ας.…”