A low latency architecture to compute the multiplicative inverse and division in a finite field GF(2 ) is presented. Compared to other proposals with the same complexity, this circuit has lower latency and can be used in error-correction or cryptography to increase system throughput. This architecture takes advantage of the simplicity to computing powers (2 ) of an element in the Galois Field. The inverse of an element is computed in two stages: power calculation and multiplication. A division can be performed using only one more multiplication in the inversion circuit.Index Terms-Finite field division, finite field inverse, finite field multiplier, VLSI architecture.